Andes Custom Extension™
Andes Custom Extension™ (ACE) lets designers design their own CPU instructions on the already performance optimized AndesCore™ processors. With ACE instructions designed specifically for the target applications, they can eliminate the software bottlenecks and significantly improve runtime performances.
Benefits of Custom Instruction Acceleration
- Hardwired speedup – use application specific instruction hardware to replace blocks of codes in the original software.
- Execution efficiency – reduce the fetch, decode, execute and retire operations of a block of instructions to those of one single ACE instruction. The improvements will be even more significant if an ACE instruction replaces program loops.
Highlights of the ACE features
- Scalar Instructions – execute in either a single cycle or multiple cycles.
- Vector Instructions – perform a loop operation such as ‘for’ or ‘do while’.
- Background instructions – retire immediately from CPU pipeline after issued, but continue the remaining execution in background to achieve parallelism.
- Standard operands – ACE instructions can utilize the operands available to the baseline instructions, including immediate constants, general purpose registers and baseline memory (accessed through CPU).
- Custom operands – Designers may also use operands based on custom-defined resources such as ACE Register (ACR) and ACE Memory (ACM). ACR and ACM can be in arbitrary width and number as applications require.
- Straightforward design flow – SoC designers create ACE definition file to describe the behavior of the ACE instructions, and concise Verilog file to design the hardware logic.
- Custom-OPtimized Instruction deveLOpment Tools (COPILOT) – a powerful but simple-to-use ACE design tool that automatically generates required extensions to development tools, ISS simulation and RTL. (Refer to the figure below.)
Benefits of using ACE for Instruction Acceleration
- The ACE design environment allows users to focus on instruction functionality, rather than on CPU pipeline and the design process.
- The COPILOT tool simplifies engineering work by directly converting the ACE design into a complete environment for the accelerated CPU.
- With ACE, adding custom instructions is more like ASIC design since it offloads housekeeping tasks such as opcode selection, instruction decoding, operand mapping/accesses, dependence checking and result gathering. All the housekeeping RTL code is generated by COPILOT.
Standard instructions do not do complex operations or wide I/O. With ACE framework, the SoC designers can do things they have already been doing with Verilog. Also using ACE is small investment to make since designers are already familiar with the C and Verilog standard languages. Powerful but simple ACE language constructs enables users to create more functions with fewer lines of Verilog code, and thus achieves outstanding performance boost and energy reduction.