Read more about the article Jmem Tek and Andes Technology Partner on the World’ s First Quantum-Secure RISC-V Chip

Jmem Tek and Andes Technology Partner on the World’ s First Quantum-Secure RISC-V Chip

Hsinchu, Taiwan – Dec 11, 2024 – Jmem Tek, a specialist in hardware security and post-quantum cryptography for IoT devices, announces a global partnership with Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor IPs and Founding Premier member of RISC-V International. Jmem Tek also joined the AndeSentry™ security collaborative framework, which offers a range of security solutions for Andes RISC-V processors, designed to counter threats from both cyber-attacks and physical attacks and enhance product security.

Jmem Tek’s PUF-based security chip, designed with Andes compact and efficient N25F RISC-V processor and Jmem Tek’s comprehensive hardware security module IP, is the world’s first NIST post-quantum cryptographic algorithm chip based on RISC-V. This collaboration brings customers an industrial-grade cyber-security solution designed to withstand future quantum computing threats.

The PUF (Physical Unclonable Function) technology in Jmem Tek’s security chip has been independently verified as robust against all known cyberattack mechanisms. PUF generates unique, unforgeable identities and cryptographic keys within microcontrollers and application-specific integrated circuits (ASICs) on-demand. These identities and keys create a root-of-trust for the chips, used in IoT devices and edge nodes. PUF eliminates the need for key injection and secure storage, fitting perfectly into the security framework embraced by the RISC-V architecture.

Jmem Tek’s hardware security module IP integrates seamlessly with the AndeSentry™ collaborative security framework, providing secure provisioning, automated onboarding to cloud platforms, security monitoring, and key lifecycle management. With a few keystrokes, customers can securely connect thousands of IoT devices to servers through cryptographic APIs.

John Chang, CEO of Jmem Tek, commented, “We are excited to partner with Andes Technology, one of the leading forces in the RISC-V ecosystem. RISC-V processors provide the foundation for the next generation of IoT devices, and our security solution complements this by ensuring data protection in the face of emerging cybersecurity threats. Together, we are pushing the boundaries of what’s possible in secure computing.”

Dr. Charlie Su, president and CTO of Andes added, “As the cyber threat landscape evolves, leading-edge processors must be equipped with leading-edge security. Jmem Tek’s PUF-based security technology is an important addition to our AndeSentry™ collaborative security framework, helping us offer best-in-class security solutions to our RISC-V customers.”

About Jmem Tek
Jmem Tek is a leader in hardware security IP and IC design, specializing in post-quantum cryptography and PUF-based technology. Their solutions protect sensitive data across a variety of industries, including IoT, AIoT, and automotive electronics. Jmem Tek’s security products ensure that companies can secure their devices and data in the quantum era and beyond.
For more information, please visit: www.jmemtek.com , and follow us on LinkedIn and X (formerly Twitter).

About Andes Technology
As a Founding Premier member of RISC-V International and a leader in commercial CPU IP, Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) is driving the global adoption of RISC-V.  Andes’ extensive RISC-V Processor IP portfolio spans from ultra-efficient 32-bit CPUs to high-performance 64-bit Out-of-Order multiprocessor coherent clusters. 
With advanced vector processing, DSP capabilities, the powerful Andes Automated Custom Extension (ACE) framework, end-to-end AI hardware/software stack, ISO 26262 certification with full compliance, and a robust software ecosystem, Andes unlocks the full potential of RISC-V, empowering customers to accelerate innovation across AI, automotive, communications, consumer electronics, data centers, and mobile devices. Over 15 billion Andes-powered SoCs are driving innovations globally.
Discover more at www.andestech.com and connect with Andes on LinkedIn, X (formerly Twitter), Bilibili and YouTube.

Continue ReadingJmem Tek and Andes Technology Partner on the World’ s First Quantum-Secure RISC-V Chip
Read more about the article HighTec C/C++ Compiler Suite Supports Andes’ ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications

HighTec C/C++ Compiler Suite Supports Andes’ ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications

Saarbrücken/Germany — Nov 28, 2024 — HighTec EDV-Systeme GmbH, a leading provider of automotive compiler solutions, has announced support for Andes’ RISC-V IP in its highly optimized C/C++ compiler for the automotive market. This support marks a milestone for automotive software developers, as HighTec’s compiler now seamlessly supports the Andes’ functional safety certified RISC-V cores to ensure optimized code generation for automotive processors, improving efficiency and performance.

Andes is committed to providing state-of-the-art automotive solutions with ISO 26262 compliant AndesCore™ RISC-V IP, software, and development tools.  In 2022, Andes launched the industry’s first certified ASIL-B RISC-V CPU IP with full compliance, the N25F-SE. Building on this achievement, Andes has expanded its Safety Enhanced (SE) series to include the DSP-capable ASIL-B D25F-SE, the streamlined and secure ASIL-D D23-SE, the high-performance ASIL-D D45-SE, and the upcoming 60-SE series targeting ADAS and IVI applications.  With certified RISC-V IP and a robust ecosystem of ISO 26262 qualified tools and software, Andes enables customers to achieve ISO 26262 certification with their end-products. The SE cores offer flexibility, scalability, security, and superior performance to meet the diverse needs of modern automotive applications.

The HighTec C/C++ compiler is built on the modern LLVM (Low Level Virtual Machine) open-source technology, and ensures optimal utilization of Andes RISC-V IP performance, enabling automotive software developers to achieve faster and more efficient code execution. Known for its fast build times, HighTec’s compiler generates highly dense and reliable code. Developers particularly value the Clang front-end for its extensive analysis options. Qualified up to ASIL D – the highest level of functional safety – HighTec’s C/C++ compiler includes a qualification toolkit that simplifies the development and certification of safety-critical applications, helping automotive software developers accelerate the certification process.

“HighTec has been committed to advancing the automotive industry for more than 20 years and is one of the world’s first ASIL certified compiler suppliers. We are pleased to add HighTec to Andes’ automotive ecosystem,” said Dr. Charlie Su, President and CTO of Andes Technology. “This latest C/C++ compiler brings significant value to our customers, offering them a differentiated, ISO 26262 certified RISC-V development environment that enhances code efficiency and performance.”

Mario Cupelli, CTO at HighTec, said, “Andes delivers the leading portfolio of ISO 26262 fully compliant RISC-V IPs, and we are excited to join their ecosystem. HighTec’s automotive compiler will provide full commitment to Andes RISC-V IP lifecycle support. Automotive customers can fast-track compliance efforts and improve the performance and robustness in safety-critical RISC-V applications, accelerating time to market for RISC-V-based automotive software solutions.”


About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.
For more information, please visit https://www.andestech.com/en/homepage. Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

 

About HighTec EDV Systeme GmbH

HighTec EDV-Systeme GmbH, Saarbruecken/Germany, is the world’s largest commercial provider of compilers using innovative open-source technologies and offers ISO 26262 ASIL D certified tools for embedded software development, the real-time operating system PXROS-HR, and a wide range of design-in services.

HighTec’s ASIL D qualified C/C++ compiler for leading multicore microcontrollers in the automotive and industrial sectors such as Arm®, TriCore™/AURIX™/TRAVEO™ families, RISC-V, Power Architecture (PowerPC) and GTM architectures are continuously adapted and optimized to new architectures in close cooperation with the silicon partners.

In addition to the multi-architecture compiler, HighTec offers PXROS-HR, a safety-certified multicore RTOS for applications with safety and multicore requirements. PXROS-HR guarantees robustness, safety, high performance, and data security in real-time environments. PXROS-HR is certified according to ISO 26262 ASIL D / IEC 61508 SIL 3 and is complemented for ASIL D development by a Tool Qualification Kit as a basis for the certification of customer applications.

Complementing this portfolio, HighTec offers development, training and consulting services.

Founded in 1982, HighTec is a privately held global company with offices in Germany, the Czech Republic, the Netherlands, Hungary and China. For more information about HighTec EDV-Systeme GmbH, visit www.hightec-rt.com.

Company Contact

HighTec EDV-Systeme GmbH

Europaallee 19

66113 Saarbrücken/Germany

Tel.: +49 681 92613-16

Email: info@hightec-rt.com

Press Contact Agency

Catherine Schneider

Mexperts AG

Tel.: +49 8143 59744-27

Email: catherine.schneider@mexperts.de
Continue ReadingHighTec C/C++ Compiler Suite Supports Andes’ ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications
Read more about the article Andes Technology Collaborates with Lauterbach to Deliver RISC-V Trace Solution

Andes Technology Collaborates with Lauterbach to Deliver RISC-V Trace Solution

HSINCHU, TAIWAN — Nov 26, 2024 — Lauterbach, the leading provider of development tools for embedded systems, and Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of RISC-V processor IP, today proudly announce their collaboration that enhances the debugging and tracing experience for engineers using Andes’ advanced NCETRACE200 trace IP with Lauterbach’s industry leading development tools TRACE32®.

With the growing demand for RISC-V architectures in various applications, the combination of Lauterbach’s TRACE32® tools and Andes’ NCETRACE200 trace solution empowers developers to have deep, non-intrusive trace visibility into their System-on-Chip (SoC) to assist debug & trace, accelerate time-to-market and achieve higher levels of reliability, performance and efficiency in their embedded products.

AndesCore™ NCETRACE200 subsystem is a non-intrusive tracing solution designed for the Andes RISC-V processor portfolio that spans from small, low-power MCUs to high-performance OoO application processors.  Key features include:

  • RISC-V N-Trace compatible trace encoder, timestamp generator and decoder
  • Multi-core tracing, up to 8 RISC-V harts
  • Configurable size Trace Buffer
  • Mixed-ISA environment supported, including compatibility with the CoreSight™ technology by Arm®.
*ARM® and CoreSight™ are trademarks or registered trademarks of ARM Limited in the United States and other countries

“We are excited to support Andes Technology trace solution with our TRACE32® tools,” said Norbert Weiss, Managing Director at Lauterbach. “Our collaboration will provide engineers with the tools they need to maximize the potential of their RISC-V designs, fostering innovation and efficiency in embedded systems.” Andes also expressed enthusiasm about the partnership. “Lauterbach is our long-term partner for many years. Working with Lauterbach allows us to deliver a comprehensive debug and trace experience to our customers, further solidifying our position in the embedded systems market,” said Dr. Charlie Su, president and CTO at Andes Technology. “This collaboration will pave the way for innovative developments in the RISC-V landscape, supporting a new generation of embedded solutions.”

 

About Lauterbach
Lauterbach is the leading manufacturer of cutting-edge development tools for embedded systems with more than 45 years of experience, serving customers all over the world and partnering with all semiconductor manufacturers. The company has played a key role in the RISC-V Foundation working groups that have defined debug and trace standards for RISC-V-based CPUs.
For more information, please visit https://www.lauterbach.com. Follow Lauterbach on LinkedIn and YouTube.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.
For more information, please visit https://www.andestech.com/en/homepage. Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

Continue ReadingAndes Technology Collaborates with Lauterbach to Deliver RISC-V Trace Solution
Read more about the article Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification

Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification

Hsinchu, Taiwan  – Oct 22, 2024  – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, proudly announces the launch of its industry-leading functional safety RISC-V processor AndesCore™ D45-SE, targeting ISO 26262 ASIL-D (Automotive Safety Integrity Level D) certification.

The D45-SE, derived from the production-proven D45, is a 32-bit, 8-stage dual-issue processor that supports the RISC-V GCBP extensions, including single/double precision FPU, 16-bit compression, bit manipulation, draft of packed SIMD/DSP extensions, and the Andes performance enhancements. Furthermore, it incorporates numerous safety features, such as dual-core lockstep (DCLS), a real-time diagnostic safety circuit that utilizes an additional processor and a set of comparators to enhance the diagnostic coverage; ECC for memory soft error protection; bus protection to secure bus transactions; a core trap status bus interface that provides real-time trap status information from the core; and StakSafe™, a hardware mechanism that  protects the stack, and maintains the same outstanding 6.12 Coremark/MHz as the D45. With these safety enhancements, the D45-SE ensures fault tolerance that meets the rigorous demands of safety-critical applications.

Additionally, it supports split-mode, allowing two cores to run independently when split-lock is configured. The processor also offers comprehensive safety documentation and support to facilitate ISO 26262 compliance, assisting customers in integrating safety features into their designs. The D45-SE marks a milestone, underscoring Andes’ commitment to providing industry -leading, mission-critical solutions for the automotive industry and beyond.

“We are thrilled to announce the D45-SE, a high-performance RISC-V processor engineered to deliver exceptional safety and reliability. It is a testament to our dedication to delivering safe and reliable solutions,” said Frankwell Lin, Andes Chairman and CEO. “This accomplishment reflects our ongoing commitment to supporting the automotive industry’s drive towards higher safety standards and innovation.”

 About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.For more information, please visit https://www.andestech.com/en/homepage  Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

Continue ReadingAndes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification
Read more about the article DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop

DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop

San Jose, CA — Oct 22, 2024 — DeepComputing, a pioneer in RISC-V innovation, today announced a strategic partnership with Andes Technology Corporation, a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores. Together, the two companies collaborate to develop the world’s first RISC-V AI PC, powered by Andes’ 7nm QiLai SoC. This innovated low-power PC will come equipped with Ubuntu Desktop and aims to redefine AI computing by combining industry-leading hardware and software designed specifically for RISC-V.

The collaboration marks a significant milestone in the evolution of AI PCs, which utilize artificial intelligence to enhance productivity, creativity, entertainment, security, and more. The power-efficient RISC-V AI PC, based on the QiLai SoC, integrates a multi-core CPU, vector processor, GPU, and various peripherals for optimal performance, and AI workload handling. This product is designed to cater to developers and enterprises looking for advanced, open-standard RISC-V solutions.

Revolutionizing AI Computing with RISC-V and Andes Technology

The Andes QiLai SoC contains 2 Andes RISC-V processors: a high-performance quad-core  AX45MP cluster and an NX27V vector processor. The AX45MP superscalar multicore is optimized for Linux-based applications by configuring a 2MB Level-2 cache and a Memory Management Unit (MMU). The NX27V vector processor, with a 512-bit vector length and data path width, is specifically designed to handle AI workloads efficiently. Running at up to 2.2 GHz (AX45MP) and 1.5 GHz (NX27V), the QiLai SoC delivers high performance while maintaining low power consumption of approximately 5W at full speed. A configuration of the AX45MP is used in the Renesas RZ/Five MPU while two instances of the NX27V help construct the PE’s (Processing Elements) in the 8×8 PE array of the Meta Training and Inference Accelerator (MTIA).

“We are excited to work with DeepComputing and Canonical for this AI PC project based on our newly-introduced QiLai SoC.” said Frankwell Lin, Chairman and CEO of Andes. “The QiLai leverages TSMC’s 7nm process technology and underscores our commitment to supporting the expansion of the RISC-V ecosystem. As always, Andes continues its position as a pure-play IP provider, not entering the chip business. Andes welcome chip company considering to license QiLai as an SoC IP for production. This AI PC project will demonstrate the power of the RISC-V architecture for general application processing and AI acceleration, and provide a powerful RISC-V platform for application development and processor IP evaluation.”

The World’s First RISC-V AI PC

The RISC-V AI PC developed by DeepComputing and Andes will feature Ubuntu Desktop. In addition, there are a suite of tools and frameworks optimized for AI workloads, including the AndeSight™ toolchains, AndeSoft™ software stacks, and AndesAIRE™ NN SDK, which compiles AI/ML models to executables running on the NX27V vector processor.

The product represents a breakthrough in AI PC design, offering an open and modular approach that caters to the growing RISC-V developer community. Designed for a wide range of use cases, the RISC-V AI PC supports diverse AI-driven applications, from productivity and creativity to gaming and security.

Gordan Markuš, Director of Silicon Alliances at Canonical noted, “We are thrilled to collaborate with DeepComputing and Andes on this groundbreaking project. By equipping the world’s first RISC-V AI PC with Ubuntu Desktop, we’re not only offering a powerful development platform but also enabling a robust, open-source software ecosystem. This partnership will help accelerate the adoption of RISC-V technology and broaden the possibilities for developers and businesses working with AI at the edge.”

Expanding the RISC-V Ecosystem

By offering the world’s first RISC-V AI PC, DeepComputing and Andes aim to accelerate the development of RISC-V-based AI solutions and expand the reach of RISC-V in the broader computing landscape. This collaboration is driven by the growing demand for RISC-V platforms that enable fast software development, evaluation, and deployment.

“We’re excited to partner with Andes Technology on this innovative project,” said Yuning, CEO of DeepComputing. “This partnership aligns with our mission to push the boundaries of RISC-V technologies and provide developers with the tools and platforms they need to shape the future of AI computing.”

The RISC-V AI PC platform will be unveiled at the RISC-V Summit NA 2024, where it will be showcased at the DeepComputing booth. The product will be officially available in early 2025.

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn、Facebook、X、Bilibili  and YouTube! 

About Canonical

Canonical, the publisher of Ubuntu, provides open source security, support and services. Their portfolio covers critical systems, from the smallest devices to the largest clouds, from the kernel to containers, from databases to AI. With customers that include top tech brands, emerging startups, governments and home users, Canonical delivers trusted open source for everyone. Learn more at https://canonical.com/.

About DeepComputing

Formed in 2022 by a group of dedicated RISC-V enthusiasts, DeepComputing is a pioneer in RISC-V innovation, leading the way in connecting developer communities, suppliers, tools and systems with the world of RISC-V. We are committed to advancing the adoption and implementation of RISC-V beyond existing ISA chipsets. Together with a diverse and dedicated array of partners, we are focused on driving development of the RISC-V ecosystem through our DeepComputing laptops, pads, workstations, AI speakers and routers, as well as our BravoMonster autonomous remote-control toys and real-world vehicles.

Continue ReadingDeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop
Read more about the article Fractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference

Fractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference

San Jose, CA — Oct. 22, 2024 — Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, are proud to announce a partnership with Fractile, the company building the chips and systems needed to reach the next frontier of AI performance. Fractile is developing AI inference accelerators based on in-memory compute, and aim to be able to run frontier AI models – large language, vision and audio models – two orders of magnitude faster than existing hardware, at a tenfold reduction in cost.

Large language models and other foundation models have become the driving force behind the skyrocketing scale of data center AI compute requirements. From ChatGPT to the open-source Llama model series, LLMs and other foundation models are finding widespread application. Model inference – the process of serving these trained models –  is coming to be the dominant portion of compute costs, exceeding the cost of model training.  Fractile has licensed the powerful Andes AX45MPV RISC-V vector processor, combined with ACE (Andes Automated Custom Extension™) and Andes Domain Library, and plans to incorporate the vector processing unit into their first generation data center AI inference accelerator.

Fractile’s uses novel circuits to execute 99.99% of the operations needed to run model inference in on-chip memory. This removes the need to shuttle model parameters to and from processor chips, instead baking computational operations into memory directly.  This architecture drives both much higher energy efficiency (TOPS/W) as well as dramatically improved latency on inference tasks (tokens per second per user in an LLM context, for instance). The company has been betting on inference scaling – leveraging more inference time-compute to improve AI performance – as the next frontier of AI scaling. The AI world seems to agree, with OpenAI recently releasing their latest LLM, o1, which requires orders of magnitude more inference compute than previous LLMs. Fractile’s hardware and software stack is built to take models that can still take many seconds to produce an answer on current hardware, and make this instantaneous.

As part of the collaboration, Fractile will integrate Andes Technology’s high-performance RISC-V vector processor with its own groundbreaking in-memory computing architecture via ACE. Fractile’s architecture leverages the strengths of both companies, aiming to deliver an exceptionally fast and cost-effective AI inference system that overcomes the limitations of conventional computing methods – blasting through the memory bottleneck.

Dr. Charlie Su, President and CTO of Andes Technology, expressed his enthusiasm for the partnership, “AX45MPV, with strong compute capabilities, high memory bandwidth and the flexible ACE tool, has been chosen by innovative AI companies large and small since its debut in 2023. Andes RISC-V vector processors have enabled many AI SoCs to break free from architecture limitation and achieve new levels of performance and efficiency. We are confident that the synergy between Fractile’s In-Memory Computing technologies and Andes’ award-winning RISC-V vector processing will lead to yet another success.”

Dr. Walter Goodwin, CEO and founder of Fractile, added: “The limitations of existing hardware present the biggest barrier to AI performance and adoption. Andes Technology has unmatched technical and commercial leadership on RISC-V vector processors and is a natural partner for us as we build Fractile’s accelerator systems. Building hardware for AI acceleration is intrinsically hard – the world’s leading models can change overnight, while chips take time to bring to market. Software-programmable vector processors like Andes’ are a key part of staying robust to these changes. We’re delighted to announce this collaboration as Fractile furthers its mission to supercharge inference.

For more information about Andes Technology and Fractile, please visit their respective websites at www.andestech.com and www.fractile.ai.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! ! 

About Fractile
Fractile is an AI hardware company that is building its first groundbreaking new AI chip, capable of running state-of-the-art AI models up to 100x faster and 10x cheaper than existing hardware. Founded in 2022 in London by 28-year-old artificial intelligence PhD Walter Goodwin, Fractile’s transformative computing technology will enhance collective AI capabilities by enabling the largest and most capable neural networks of today and tomorrow to run faster, more efficiently and more sustainably. The company has raised $17.5m (£14m) in funding from investors including the NATO Innovation Fund, Kindred Capital, Oxford Science Enterprises, Cocoa and Inovia Capital, as well as angel investors including Hermann Hauser (founder, Acorn, Amadeus), Stan Boland (ex-Acorn, Icera, NVIDIA and Five AI) and Amar Shah (co-founder, Wayve).

Continue ReadingFractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference
Read more about the article Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension

Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension

Hsinchu, Taiwan – Oct 21, 2024 – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the AndesCore™ 46-series processor family with 4 members. The first member, AX46MPV, a new 64-bit multicore superscalar vector processor IP, is the third generation of the award-winning Andes Vector core. While it maintains the same 8-stage dual-issue pipeline as its predecessor AX45MPV, it incorporates numerous new features such as dual load/store units, private L2 cache, an extended VLEN, Andes Matrix Multiply Extension, and RVA22 profile support. Except vector and matrix support, the second member, AX46MP, has the exact same features as the AX46MPV while the third member, A46MP, and fourth member, A46MPV, are the 32-bit versions of AX46MP and AX46MPV. This makes the 46-series ideal for network processors running Linux, high-performance embedded controllers requiring high memory throughput, and large-scale AI/ML applications.

The AX46MPV enhances SpecInt2006 performance by over 15% compared to the previous generation AX45MPV, thanks to its newly designed memory subsystem. The private L2 cache significantly reduces memory latency while the dual load/store engine eliminates memory bottlenecks in memory-bound computation kernels. It supports up to 16 cores in the same cluster, featuring cache coherence and a shared L3 cache with doubled capacity of the AX45MPV. Additionally, the AX46MPV provides TrustZone-level security with ePMP and IOPMP, accompanied by a pre-integrated software solution.

The AX46MPV introduces several enhancements for AI/ML, including longer 2048-bit vectors, new Andes Matrix Extensions to efficiently speed up GEMM performance, and greatly improved High-Bandwidth Vector Memory (HVM) interface supporting outstanding requests and out-of-order responses. A high-performance HVM controller serving up to 16 cores and DMA accesses with 64 memory banks is optional for licensing. The AX46MPV now also includes BF16 full arithmetic mode as a standard feature. Additionally, the award-winning Andes Automated Custom Extension™ (ACE) is available in the 46-series, featuring customized vector instructions (ACE_RVV) with enhanced pipeline and Streaming Port (ASP).  

“We are thrilled to introduce the 3rd generation of the Andes Vector series, further strengthening our leadership in the AI SoC market,” said Dr. Charlie Su, President and CTO of Andes Technology. “Our NX27V and AX45MPV have been highly successful in high-performance AI SoC applications. The AX46MPV, boosted with both compute performance and memory bandwidth, is intended to bring the new-generation AI SoCs to the next level of compute density. Additionally, with enhanced capabilities in Linux, security, and AIoT, the highly configurable 46-series is a well-rounded solution with balanced performance, power, and area”

The AndesCore™ 46-series processor IP’s, 64-bit AX46MP(V) and 32-bit A46MP(V), can be configured from one core up to 16 cores. It is to be available for lead customers in Q1 2025 through the early access program and for general customers in Q2 2025. For further information about the Andes 46 series and Vector processors, please contact Andes Technology.

About Andes Technology

Nineteen years in business and a founding premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

Continue ReadingAndes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension
Read more about the article Andes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android

Andes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android

Hsinchu, Taiwan — Oct 18, 2024 — Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the AndesCore™ AX66 out-of-order superscalar multicore processor IP supporting the RVA23 profile. The AX66 is the 2nd member of the high-performance out-of-order AX60 series. Built on the success of the AX65 with the same 13-stage pipeline, 4-wide decode, and 8-wide out-of-order execution, the AX66 introduces many new features, including Vector and Vector Crypto support, Hypervisor and AIA, Multi-Cluster support with CHI, and RVA23 profile support. AX66’s versatile capabilities on performance scalability, multimedia, security, and virtualization makes it an ideal main processor in high-performance Linux and Android applications such as edge/data center AI, infotainment, networking, and vision/camera applications.

The AX66 boosts the SpecInt2006 performance over the 1st generation AX65 by more than 15%. Each core has 64KB private L1 instruction and data caches and up to 1MB private L2 cache, and each cluster contains up to 8 cores and a shared L3 cache up to 32MB. Besides the IO coherence interface already in the AX65, the AX66 adds a Coherence Hub Interface (CHI) for multi-cluster coherence. With the CHI interface support, we can use much more AX66 CPUs to work together in the same cache-coherent domain.  Together with the Hypervisor, AIA and optional IOMMU technologies, the AX66 can fully virtualize the entire multi-cluster CPU subsystem for resource sharing and security. Moreover, the AX66 supports the RISC-V standard external debug and instruction trace interfaces to facilitate fast system development, analysis and debugging.

“We are excited to announce our 2nd member of the top-of-the-line AX60 series, to further expand our portfolio,” said Dr. Charlie Su, President and CTO of Andes Technology. “We have added numerous features to the AX66, enabling its usage across a wide range of applications. With the RVV support, the AX66 can now handle more advanced AI/ML and multimedia applications. The inclusion of the Vector Crypto extension and the optional IOMMU provides the security capability for a modern day platform system. Additionally, the Hypervisor, AIA, CHI interface support make the AX66 suitable for the data center network applications such as Smart NIC or Data Processing Unit(DPU), and edge servers or devices running containerized applications. The inclusion of the RVA23 profile allows the AX66 to run Android OS on wearables, POS terminals, digital signage, and TV set-top boxes. We anticipate the AX66 to further penetrate high-end mainstream markets.”

The AndesCore™ AX66 is to be available for lead customers in Q4 2024 through the early access program and for general customers in 2025. For further information about the AX66 and the AX60 series processors, please contact Andes Technology.

 

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com . Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

Continue ReadingAndes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android
Read more about the article TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor

TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor

By Wenbo Yin, Vice President of IC Design, TetraMem Inc.

Introduction
The rapid proliferation of artificial intelligence (AI) across a growing number of hardware applications has driven an unprecedented demand for specialized compute acceleration not met by conventional von Neumann architectures. Among the competing alternatives, one showing the greatest promise is analog in-memory computing (IMC). Unleashing the potential of multi-level Resistive RAM (RRAM) is making the promise more real today than in the past. Leading this development, TetraMem, Inc., a Silicon Valley based startup, is addressing the fundamental challenges holding this solution back. The company’s unique IMC that employs multi-level RRAM technology provides more efficient, low-latency AI processing that meets the growing needs of modern applications in AR/VR, mobile, IoT, and beyond.

Background on the Semiconductor Industry
The semiconductor industry has seen significant advancements over the past few decades, particularly in response to the burgeoning needs of AI and machine learning (ML). Innovations in chip design have pushed the boundaries of performance and efficiency. However, several intrinsic persistent challenges remain, such as the von Neumann bottleneck and memory wall, which limits data transfer rates between the CPU and memory, and the escalating power consumption and thermal management issues associated with advanced node technologies.

In-memory computing (IMC) represents a ground-breaking computing paradigm shift in how data processing is accomplished. Traditional computing architectures separate memory and processing units, resulting in significant data transfer overheads, especially for the data centric AI applications. On the other hand, IMC integrates memory and processing within the same physical location, enabling faster and more efficient data computations with a crossbar array architecture to further eliminate the large quantity of intermediate data from those matrix operations. This approach is particularly beneficial for AI and ML applications, where large-scale data processing and real-time analytics are critical.

Selecting a suitable memory device for IMC is crucial. Traditional memory technologies like SRAM and DRAM are not optimized for in-memory operations due to their device and cell constraints and their volatility idiosyncrasies. RRAM, with its high density, multilevel capability and non-volatility with superior retention, overcomes these challenges with no refresh needed. The working principle of RRAM involves adjusting the resistance level of the memory cell through controlled voltage or current, mimicking the behavior of synapses in the human brain. This capability makes RRAM particularly suited for analog in-memory computing.

TetraMem has focused its efforts on multi-level RRAM (memristor) technology, which offers several advantages over traditional single level cell memory technologies. RRAM’s ability to store multiple bits per cell and perform efficient matrix multiplications in situ makes it an ideal candidate for IMC. This technology addresses many of the limitations of conventional digital computing, such as bandwidth constraints and power inefficiency.

The RRAM programmable circuit element remembers its last stable resistance level. This resistance level can be adjusted by applying voltage or current. Changes in magnitude and direction of voltage and current applied to the element alters its conductance, thus changing its resistivity. Akin to how a human neuron functions, this mechanism has diverse applications: memory, analog neuron, and, at TetraMem, in-memory computing. The operation of an RRAM is driven by ions. With control of the conductive filament size, ion concentration and height, different multi-levels for cell resistance can be precisely achieved.

Data processed in the same physical location as it is stored with minimum intermediate data movement and storage results in low power consumption. Massive parallel computing by crossbar array architecture with device-level grain cores yields high throughput. And computing by physical laws in this way (Ohm’s law and Kirchhoff’s current law) produces low latency. TetraMem’s nonvolatile compute in-memory cell reduces power consumption by orders of magnitude over a conventional digital von Neumann architecture.

Notable Achievements
TetraMem has achieved significant milestones in the development of RRAM technology. Notably, the company has demonstrated an unprecedented device with 11 bits per cell, achieving over 2,000 levels in a single element. This level of precision represents a major breakthrough in memory compute technology.

Recent publications in prestigious journals such as Nature1 and Science2 highlight TetraMem’s innovative approaches. Techniques to improve cell noise performance and to enhance multi-level IMC have been key areas of advancement. For example, TetraMem has developed proprietary algorithms to suppress random telegraph noise, resulting in superior memory retention and endurance characteristics for RRAM cells.

Operation of IMC
TetraMem’s IMC technology utilizes a crossbar architecture, where each cross-point in the array corresponds to a programmable RRAM memory cell. This configuration allows for highly parallel operations, which are essential for neural network computations. During a Vector-Matrix Multiplication (VMM) operation, input activations are applied to the crossbar array, and the resulting computations are collected on the bit lines. This method significantly reduces the need to transfer data between memory and processing units, thereby enhancing computational efficiency.

Real-World Applications
TetraMem’s first evaluation SoC through the commercial fab process, the MX100 chip (see figure) exemplifies the practical applications of its IMC technology. The chip has been demonstrated in various on-chip demos, showcasing its capabilities in real-world scenarios. One notable demo, the Pupil Center Net (PCN), illustrates the chip’s application in AR/VR for face tracking and authentication monitoring in autonomous vehicles.

To facilitate the adoption of its technology, TetraMem provides a comprehensive Software Development Kit (SDK). This SDK enables developers to define edge AI models seamlessly. Furthermore, the integration with Andes Technology Inc.’s NX27V RISC-V CPU with Vector extensions streamlines operations, making it easier for customers to deploy TetraMem’s solutions in their products.

The TetraMem IMC design is great for matrix multiplication but not as efficient in other functions such as vector or scalar operations. These operations are used frequently in neural networks.  For these functions, Andes provides the flexibility of a CPU plus a vector engine as well as an existing SoC reference design and a mature compiler and library to accelerate our time to market.

TetraMem collaborated with Andes Technology to integrate its IMC technology with Andes’ RISC-V CPU with Vector Extensions. This partnership enhances the overall system performance, providing a robust platform for a variety of AI tasks. The combined solution leverages the strengths of both companies, offering a flexible and high-performance architecture.

Looking ahead, TetraMem is poised to introduce the MX200 chip based on 22nm, which promises even greater performance and efficiency. This chip is designed for edge inference applications, offering low-power, low-latency AI processing. The MX200 is expected to open new market opportunities, particularly in battery-powered AI devices where energy efficiency is paramount.

Conclusion
TetraMem’s advancements in in-memory computing represent a significant leap forward in the field of AI hardware. By addressing the fundamental challenges of conventional computing, TetraMem is paving the way for more efficient and scalable AI solutions. As the company continues to innovate and collaborate with industry leaders like Andes Technology, the future of AI processing looks promising. TetraMem’s solution not only enhances performance but also lowers the barriers to entry for adopting cutting-edge AI technologies.

  1. “Thousands of conductance levels in memristors monolithically integrated on CMOS”, Nature, Mar 2023 https://rdcu.be/c8GWo
  2. “Programming memristor arrays with arbitrarily high precision for analog computing”, Science, Feb 2024 https://www.science.org/doi/10.1126/science.adi9405
Continue ReadingTetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector Processor
Read more about the article Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC

Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC

NX45 Becomes the Only RISC-V Core to Pass Rivos’ Rigorous Verification Process After Extensive Evaluation of Leading RISC-V Cores

San Jose, CA – Sep. 11, 2024— Rivos Inc., a RISC-V Premier member company focused on accelerating data analytics and Generative AI workloads and Andes Technology, a leading supplier of 32/64-bit RISC-V processor cores and a RISC-V Founding Premier member , announced that Rivos Inc. has licensed the Andes NX45 RISC-V Processor for key control functions in their products.

Rivos was founded in 2021 by industry veterans from Google, Intel, Apple, and PA-Semi and has assembled a world class team of silicon, software, and platform engineers to build industry-leading power efficient, high performance, secure server solutions based on a high-end internally developed RISC-V CPU. 

To run control and scheduling for several key functions in Rivos’ SoC, the highly configurable and extensible Andes NX45 RISC-V processor was chosen because it allows the best tradeoffs in performance and efficiency, while meeting the highest quality standards.

“We are excited to welcome Rivos Inc. to the RISC-V community and wish them tremendous success,” said Dr. Charlie Su, President & CTO of Andes Technology. “We are proud that Rivos chose the NX45 for their project. Rivos’ selection of Andes is a testament to our flexibility, development rigor, and dedication to quality.”

“The growth of the RISC-V ecosystem and customer traction has been remarkable, and we are thrilled to be part of this movement,” said Belli Kuttanna, Co-Founder and CTO at Rivos Inc. “After evaluating several leading RISC-V cores, the Andes NX45 stood out as the only core that passed our proprietary verification process with zero bugs. Its robust configuration options and ease of integration made it the clear choice as our 64-bit control core.”

Rivos recently raised over $250M in an oversubscribed series A-3 funding round to enable the company to tape out its first silicon product, expand manufacturing operations, and scale platform hardware and software engineering efforts.

Andes Technology has been delivering a full range of processing solutions for over 19 years.  Launched in 2019, the AndesCore™ 45-series includes in-order 8-stage dual-issue RISC-V processors with options to support multicore, Linux, and vector processing to meet the demands of many high-end applications.  Andes’ customers benefit from a full-product offering including AndeSight™ IDE, Andes Custom Extension™ (ACE) and related software, and modeling, debug, and trace tools to accelerate their SoC development.

About Rivos Inc.
Rivos has assembled a world class team of silicon, software and platform designers implementing the long term vision of building industry-leading power efficient, high performance, secure server solutions, based on RISC-V, using workload-defined hardware. Rivos supports the intense requirements of the large language models and data analytics through a full solution of optimized chips; combining RISC-V CPUs, a Data Parallel Accelerator, and a reference multi-chip OCP modular server along with a full firmware-to-application open software stack. Rivos is hiring engineering talent across multiple disciplines.

About Andes Technology
Nineteen years in business and a Founding Premier member of RISC-V International, Andes is publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn、Facebook、X、Bilibili  and YouTube! 

 

Continue ReadingRivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC