Job Opportunities
In order to seize the market of profitable high-end multicore CPU IPs and boost sales momentum, Andes’ design centers in Taiwan, United States and Canada plan to recruit 200 R&D talents to develop the next-generation RISC-V products for applications including 5G, artificial intelligence/machine learning, HPC, ADAS, automotive electronics, AR /VR, blockchain, cloud computing, data center, server, Internet of Things, MCU, storage devices, security, wireless devices, and other massive and high-performance computing markets.
Taiwan
- We have offices in Hsinchu and Taipei. See 104.com.tw for a complete listing of current job offerings.
North America
We have offices in San Jose, California and Portland, Oregon.
We also offer remote work options. Visit our LinkedIn or refer to the list below for job opportunities.
Role
This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the opportunity to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.
As a leader of this team, you will define verification methodologies, analyze problems, and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. You will have the opportunity to mentor junior members of the team. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.
Daily activity includes:
-
Mentor/teach other verification members in their approaches
-
Track schedule and project status
-
Communication with team members to discuss technical details
-
Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them
-
Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports
-
Hands-on verification work including verification regression management, debugging and bug-reports
-
Technical documentation
Technical Requirements
-
Bachelor’s or Master’s degree in related engineering field
-
Proven track record for verifying designs to tape out quality
-
Strong communication and leadership skills
-
Experience using Verilog, System Verilog, UVM, coverage analysis, formal
-
Strong mastery using Unix and scripting languages such as make, shell, perl or python
-
Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug)
Desirable Skills
-
Experience coding in assembly languages
-
Strong desire to learn and willing to devote extra effort to achieve perfection
-
Strong team player and possess a positive attitude
-
Multi-lingual
-
Cross-site or multi-time zone experience
-
Good time management skills
Role
You will be a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.
As a senior member of this team, you will help guide verification methodologies, analyze problems and devise best QoR solutions. You will participate in engineering discussions and be expected to drive analysis and propose directions. Applicants of this role would be diligent, detail oriented and have a penchant for creating high-quality results efficiently. You should also admire technical advances, CPU architecture and have a keen interest in tackling present day verification problems.
Daily activity includes:
Communication with peers to discuss technical details
Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them
Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports
Hands-on verification work including verification regression management, debugging and bug-reports
Provide technical guidance to junior members of the team
Technical documentation
Technical Requirements
Bachelor’s or Master’s degree in related engineering field
Strong communication skills
Experience using Verilog, System Verilog
Strong mastery using Unix and scripting languages such as make, shell, perl or python
Desirable Skills
Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug)
Experience coding in assembly languages
Experience in UVM, formal, coverage grading, coverage analysis, bug tracking
Patience and good leadership skills
Strong desire to learn and willing to devote extra effort to achieve perfection
Strong team player and possess a positive attitude
Role
This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the chance to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.
As a member of this team, you will help guide verification methodologies, analyze problems and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.
Daily activity includes:
Communication with peers to discuss technical details
Competitive analysis and critique pros and cons, such as the balance of performance, area, power
Explicit CPU hardware design ranging such as fetch units, scheduling, complex vector or floating-point maths, load-store units, coherent memory access or multi-core debug architecture
Design quality analysis including synthesis to assess frequency, area, power quality
Providing technical guidance to junior members of the team
Technical documentation
Technical Requirements
Over 3 years for Mid level/10 years for Senior level of applicable work experience
Bachelor’s or Master’s degree in related engineering field
Strong communication skills
Experience in bus protocols such as AXI, CHI
Experience of ASIC design techniques, pipelines and basic CPU microarchitecture
Experience in synthesis, physical layout concepts, static timing analysis, clock domain crossing
Strong mastery using Verilog, System Verilog
Strong mastery using Unix and scripting languages such as make, shell, perl or python
Additional Technical Requirements for Senior Level:
Experience of advanced CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug) and assembly languages
Desirable Skills
Patience and good leadership skills
Strong desire to learn and willing to devote extra effort to achieve perfection
Strong team player and possess a positive attitude
Experience or knowledge in verification techniques such as UVM, formal, coverage analysis, bug tracking
Role
This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the opportunity to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.
As a member of this team, you will help guide verification methodologies, analyze problems and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.
Daily activity includes:
Communication with peers to discuss technical details
Competitive analysis and critique pros and cons, such as the balance of performance, area, power
Explicit CPU hardware design ranging such as fetch units, scheduling, complex vector or floating-point maths, load-store units, coherent memory access or multi-core debug architecture
Design quality analysis including synthesis to assess frequency, area, power quality
Providing technical guidance to junior members of the team
Technical documentation
Technical Requirements
Over 3 years for Mid level/10 years for Senior level of applicable work experience
Bachelor’s or Master’s degree in related engineering field
Strong communication skills
Experience in bus protocols such as AXI, CHI
Experience of ASIC design techniques, pipelines and basic CPU microarchitecture
Experience in synthesis, physical layout concepts, static timing analysis, clock domain crossing
Strong mastery using Verilog, System Verilog
Strong mastery using Unix and scripting languages such as make, shell, perl or python
Additional Technical Requirements for Senior Level:
Experience of advanced CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug) and assembly languages
Desirable Skills
Patience and good leadership skills
Strong desire to learn and willing to devote extra effort to achieve perfection
Strong team player and possess a positive attitude
Experience or knowledge in verification techniques such as UVM, formal, coverage analysis, bug tracking
Role
This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the opportunity to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.
As a member of this team, you will help guide verification methodologies, analyze problems and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.
Daily activity includes:
Communication with peers to discuss technical details
Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them
Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports
Hands-on verification work including verification regression management, debugging and bug-reports
Provide technical guidance to junior members of the team
Technical documentation
Technical Requirements
Bachelor’s or Master’s degree in related engineering field
Strong communication skills
Experience using Verilog, System Verilog
Strong mastery using Unix and scripting languages such as make, shell, perl or python
Desirable Skills
Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug)
Experience coding in assembly languages
Experience in UVM, formal, coverage grading, coverage analysis, bug tracking
Patience and good leadership skills
Strong desire to learn and willing to devote extra effort to achieve perfection
Strong team player and possess a positive attitude
Role
This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the opportunity to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.
As a leader of this team, you will define verification methodologies, analyze problems, and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. You will have the opportunity to mentor junior members of the team. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.
Daily activity includes:
Mentor/teach other verification members in their approaches
Track schedule and project status
Communication with team members to discuss technical details
Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them
Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports
Hands-on verification work including verification regression management, debugging and bug-reports
Technical documentation
Technical Requirements
Bachelor’s or Master’s degree in related engineering field
Proven track record for verifying designs to tape out quality
Strong communication and leadership skills
Experience using Verilog, System Verilog, UVM, coverage analysis, formal
Strong mastery using Unix and scripting languages such as make, shell, perl or python
Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug)
Desirable Skills
Experience coding in assembly languages
Strong desire to learn and willing to devote extra effort to achieve perfection
Strong team player and possess a positive attitude
Multi-lingual
Cross-site or multi-time zone experience
Good time management skills
Role
This role is a part of the VLSI team, which is part of Andes worldwide CPU development team. Andes is a rapidly growing organization, and you will get the opportunity to work with a team of experienced architects, designers and DV engineers for building next-generation of RISC-V CPUs.
As a senior member of this team, you will help guide verification methodologies, analyze problems and devise best QoR solutions. You will be able to participate in engineering discussions and drive analysis and propose directions. We value diligence, detail orientation and a penchant for creating high-quality results efficiently. Ideal applicants will have a passion for technical advances, CPU architecture and have a keen interest in tackling present day verification problems.
Daily activity includes:
Communication with peers to discuss technical details
Analyze CPU architecture and microarchitecture implementations, and devising best methods to verify them
Identify and resolve engineering issues ranging from functional verification, code coverage, Formal proofs, verification reports
Hands-on verification work including verification regression management, debugging and bug-reports
Provide technical guidance to junior members of the team
Technical documentation
Technical Requirements
Over 3 years of applicable work experience
Bachelor’s or Master’s degree in related engineering field
Strong communication skills
Experience using Verilog, System Verilog
Strong mastery using Unix and scripting languages such as make, shell, perl or python
Experience in Formal Property Verification
Experience in Formal Coverage Analysis
Experience in the use of Formal tools such as JasperGold of FPV
Experience of CPU architecture (multi-core coherence, FPU, DSP, interrupt, Vector, Security, Reset and CDC, Debug)
Desirable Skills
Experience coding in assembly languages
Experience in UVM, formal, coverage grading, coverage analysis, bug tracking
Patience and good leadership skills
Strong desire to learn and willing to devote extra effort to achieve perfection
Strong team player and possess a positive attitude
Seniority Level
Associate
Global Offices
- We offer remote work options. For more information, contact our global recruiter at hr@andestech.com.