Read more about the article HighTec C/C++ Compiler Suite Supports Andes’ ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications

HighTec C/C++ Compiler Suite Supports Andes’ ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications

Saarbrücken/Germany — Nov 28, 2024 — HighTec EDV-Systeme GmbH, a leading provider of automotive compiler solutions, has announced support for Andes’ RISC-V IP in its highly optimized C/C++ compiler for the automotive market. This support marks a milestone for automotive software developers, as HighTec’s compiler now seamlessly supports the Andes’ functional safety certified RISC-V cores to ensure optimized code generation for automotive processors, improving efficiency and performance.

Andes is committed to providing state-of-the-art automotive solutions with ISO 26262 compliant AndesCore™ RISC-V IP, software, and development tools.  In 2022, Andes launched the industry’s first certified ASIL-B RISC-V CPU IP with full compliance, the N25F-SE. Building on this achievement, Andes has expanded its Safety Enhanced (SE) series to include the DSP-capable ASIL-B D25F-SE, the streamlined and secure ASIL-D D23-SE, the high-performance ASIL-D D45-SE, and the upcoming 60-SE series targeting ADAS and IVI applications.  With certified RISC-V IP and a robust ecosystem of ISO 26262 qualified tools and software, Andes enables customers to achieve ISO 26262 certification with their end-products. The SE cores offer flexibility, scalability, security, and superior performance to meet the diverse needs of modern automotive applications.

The HighTec C/C++ compiler is built on the modern LLVM (Low Level Virtual Machine) open-source technology, and ensures optimal utilization of Andes RISC-V IP performance, enabling automotive software developers to achieve faster and more efficient code execution. Known for its fast build times, HighTec’s compiler generates highly dense and reliable code. Developers particularly value the Clang front-end for its extensive analysis options. Qualified up to ASIL D – the highest level of functional safety – HighTec’s C/C++ compiler includes a qualification toolkit that simplifies the development and certification of safety-critical applications, helping automotive software developers accelerate the certification process.

“HighTec has been committed to advancing the automotive industry for more than 20 years and is one of the world’s first ASIL certified compiler suppliers. We are pleased to add HighTec to Andes’ automotive ecosystem,” said Dr. Charlie Su, President and CTO of Andes Technology. “This latest C/C++ compiler brings significant value to our customers, offering them a differentiated, ISO 26262 certified RISC-V development environment that enhances code efficiency and performance.”

Mario Cupelli, CTO at HighTec, said, “Andes delivers the leading portfolio of ISO 26262 fully compliant RISC-V IPs, and we are excited to join their ecosystem. HighTec’s automotive compiler will provide full commitment to Andes RISC-V IP lifecycle support. Automotive customers can fast-track compliance efforts and improve the performance and robustness in safety-critical RISC-V applications, accelerating time to market for RISC-V-based automotive software solutions.”


About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.
For more information, please visit https://www.andestech.com/en/homepage. Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

 

About HighTec EDV Systeme GmbH

HighTec EDV-Systeme GmbH, Saarbruecken/Germany, is the world’s largest commercial provider of compilers using innovative open-source technologies and offers ISO 26262 ASIL D certified tools for embedded software development, the real-time operating system PXROS-HR, and a wide range of design-in services.

HighTec’s ASIL D qualified C/C++ compiler for leading multicore microcontrollers in the automotive and industrial sectors such as Arm®, TriCore™/AURIX™/TRAVEO™ families, RISC-V, Power Architecture (PowerPC) and GTM architectures are continuously adapted and optimized to new architectures in close cooperation with the silicon partners.

In addition to the multi-architecture compiler, HighTec offers PXROS-HR, a safety-certified multicore RTOS for applications with safety and multicore requirements. PXROS-HR guarantees robustness, safety, high performance, and data security in real-time environments. PXROS-HR is certified according to ISO 26262 ASIL D / IEC 61508 SIL 3 and is complemented for ASIL D development by a Tool Qualification Kit as a basis for the certification of customer applications.

Complementing this portfolio, HighTec offers development, training and consulting services.

Founded in 1982, HighTec is a privately held global company with offices in Germany, the Czech Republic, the Netherlands, Hungary and China. For more information about HighTec EDV-Systeme GmbH, visit www.hightec-rt.com.

Company Contact

HighTec EDV-Systeme GmbH

Europaallee 19

66113 Saarbrücken/Germany

Tel.: +49 681 92613-16

Email: info@hightec-rt.com

Press Contact Agency

Catherine Schneider

Mexperts AG

Tel.: +49 8143 59744-27

Email: catherine.schneider@mexperts.de
Continue ReadingHighTec C/C++ Compiler Suite Supports Andes’ ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications
Read more about the article Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification

Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification

Hsinchu, Taiwan  – Oct 22, 2024  – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, proudly announces the launch of its industry-leading functional safety RISC-V processor AndesCore™ D45-SE, targeting ISO 26262 ASIL-D (Automotive Safety Integrity Level D) certification.

The D45-SE, derived from the production-proven D45, is a 32-bit, 8-stage dual-issue processor that supports the RISC-V GCBP extensions, including single/double precision FPU, 16-bit compression, bit manipulation, draft of packed SIMD/DSP extensions, and the Andes performance enhancements. Furthermore, it incorporates numerous safety features, such as dual-core lockstep (DCLS), a real-time diagnostic safety circuit that utilizes an additional processor and a set of comparators to enhance the diagnostic coverage; ECC for memory soft error protection; bus protection to secure bus transactions; a core trap status bus interface that provides real-time trap status information from the core; and StakSafe™, a hardware mechanism that  protects the stack, and maintains the same outstanding 6.12 Coremark/MHz as the D45. With these safety enhancements, the D45-SE ensures fault tolerance that meets the rigorous demands of safety-critical applications.

Additionally, it supports split-mode, allowing two cores to run independently when split-lock is configured. The processor also offers comprehensive safety documentation and support to facilitate ISO 26262 compliance, assisting customers in integrating safety features into their designs. The D45-SE marks a milestone, underscoring Andes’ commitment to providing industry -leading, mission-critical solutions for the automotive industry and beyond.

“We are thrilled to announce the D45-SE, a high-performance RISC-V processor engineered to deliver exceptional safety and reliability. It is a testament to our dedication to delivering safe and reliable solutions,” said Frankwell Lin, Andes Chairman and CEO. “This accomplishment reflects our ongoing commitment to supporting the automotive industry’s drive towards higher safety standards and innovation.”

 About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.For more information, please visit https://www.andestech.com/en/homepage  Follow Andes on Twitter, LinkedIn, YouTube and Facebook.

Continue ReadingAndes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification
Read more about the article DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop

DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop

San Jose, CA — Oct 22, 2024 — DeepComputing, a pioneer in RISC-V innovation, today announced a strategic partnership with Andes Technology Corporation, a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores. Together, the two companies collaborate to develop the world’s first RISC-V AI PC, powered by Andes’ 7nm QiLai SoC. This innovated low-power PC will come equipped with Ubuntu Desktop and aims to redefine AI computing by combining industry-leading hardware and software designed specifically for RISC-V.

The collaboration marks a significant milestone in the evolution of AI PCs, which utilize artificial intelligence to enhance productivity, creativity, entertainment, security, and more. The power-efficient RISC-V AI PC, based on the QiLai SoC, integrates a multi-core CPU, vector processor, GPU, and various peripherals for optimal performance, and AI workload handling. This product is designed to cater to developers and enterprises looking for advanced, open-standard RISC-V solutions.

Revolutionizing AI Computing with RISC-V and Andes Technology

The Andes QiLai SoC contains 2 Andes RISC-V processors: a high-performance quad-core  AX45MP cluster and an NX27V vector processor. The AX45MP superscalar multicore is optimized for Linux-based applications by configuring a 2MB Level-2 cache and a Memory Management Unit (MMU). The NX27V vector processor, with a 512-bit vector length and data path width, is specifically designed to handle AI workloads efficiently. Running at up to 2.2 GHz (AX45MP) and 1.5 GHz (NX27V), the QiLai SoC delivers high performance while maintaining low power consumption of approximately 5W at full speed. A configuration of the AX45MP is used in the Renesas RZ/Five MPU while two instances of the NX27V help construct the PE’s (Processing Elements) in the 8×8 PE array of the Meta Training and Inference Accelerator (MTIA).

“We are excited to work with DeepComputing and Canonical for this AI PC project based on our newly-introduced QiLai SoC.” said Frankwell Lin, Chairman and CEO of Andes. “The QiLai leverages TSMC’s 7nm process technology and underscores our commitment to supporting the expansion of the RISC-V ecosystem. As always, Andes continues its position as a pure-play IP provider, not entering the chip business. Andes welcome chip company considering to license QiLai as an SoC IP for production. This AI PC project will demonstrate the power of the RISC-V architecture for general application processing and AI acceleration, and provide a powerful RISC-V platform for application development and processor IP evaluation.”

The World’s First RISC-V AI PC

The RISC-V AI PC developed by DeepComputing and Andes will feature Ubuntu Desktop. In addition, there are a suite of tools and frameworks optimized for AI workloads, including the AndeSight™ toolchains, AndeSoft™ software stacks, and AndesAIRE™ NN SDK, which compiles AI/ML models to executables running on the NX27V vector processor.

The product represents a breakthrough in AI PC design, offering an open and modular approach that caters to the growing RISC-V developer community. Designed for a wide range of use cases, the RISC-V AI PC supports diverse AI-driven applications, from productivity and creativity to gaming and security.

Gordan Markuš, Director of Silicon Alliances at Canonical noted, “We are thrilled to collaborate with DeepComputing and Andes on this groundbreaking project. By equipping the world’s first RISC-V AI PC with Ubuntu Desktop, we’re not only offering a powerful development platform but also enabling a robust, open-source software ecosystem. This partnership will help accelerate the adoption of RISC-V technology and broaden the possibilities for developers and businesses working with AI at the edge.”

Expanding the RISC-V Ecosystem

By offering the world’s first RISC-V AI PC, DeepComputing and Andes aim to accelerate the development of RISC-V-based AI solutions and expand the reach of RISC-V in the broader computing landscape. This collaboration is driven by the growing demand for RISC-V platforms that enable fast software development, evaluation, and deployment.

“We’re excited to partner with Andes Technology on this innovative project,” said Yuning, CEO of DeepComputing. “This partnership aligns with our mission to push the boundaries of RISC-V technologies and provide developers with the tools and platforms they need to shape the future of AI computing.”

The RISC-V AI PC platform will be unveiled at the RISC-V Summit NA 2024, where it will be showcased at the DeepComputing booth. The product will be officially available in early 2025.

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn、Facebook、X、Bilibili  and YouTube! 

About Canonical

Canonical, the publisher of Ubuntu, provides open source security, support and services. Their portfolio covers critical systems, from the smallest devices to the largest clouds, from the kernel to containers, from databases to AI. With customers that include top tech brands, emerging startups, governments and home users, Canonical delivers trusted open source for everyone. Learn more at https://canonical.com/.

About DeepComputing

Formed in 2022 by a group of dedicated RISC-V enthusiasts, DeepComputing is a pioneer in RISC-V innovation, leading the way in connecting developer communities, suppliers, tools and systems with the world of RISC-V. We are committed to advancing the adoption and implementation of RISC-V beyond existing ISA chipsets. Together with a diverse and dedicated array of partners, we are focused on driving development of the RISC-V ecosystem through our DeepComputing laptops, pads, workstations, AI speakers and routers, as well as our BravoMonster autonomous remote-control toys and real-world vehicles.

Continue ReadingDeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop
Read more about the article Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension

Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension

Hsinchu, Taiwan – Oct 21, 2024 – Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the AndesCore™ 46-series processor family with 4 members. The first member, AX46MPV, a new 64-bit multicore superscalar vector processor IP, is the third generation of the award-winning Andes Vector core. While it maintains the same 8-stage dual-issue pipeline as its predecessor AX45MPV, it incorporates numerous new features such as dual load/store units, private L2 cache, an extended VLEN, Andes Matrix Multiply Extension, and RVA22 profile support. Except vector and matrix support, the second member, AX46MP, has the exact same features as the AX46MPV while the third member, A46MP, and fourth member, A46MPV, are the 32-bit versions of AX46MP and AX46MPV. This makes the 46-series ideal for network processors running Linux, high-performance embedded controllers requiring high memory throughput, and large-scale AI/ML applications.

The AX46MPV enhances SpecInt2006 performance by over 15% compared to the previous generation AX45MPV, thanks to its newly designed memory subsystem. The private L2 cache significantly reduces memory latency while the dual load/store engine eliminates memory bottlenecks in memory-bound computation kernels. It supports up to 16 cores in the same cluster, featuring cache coherence and a shared L3 cache with doubled capacity of the AX45MPV. Additionally, the AX46MPV provides TrustZone-level security with ePMP and IOPMP, accompanied by a pre-integrated software solution.

The AX46MPV introduces several enhancements for AI/ML, including longer 2048-bit vectors, new Andes Matrix Extensions to efficiently speed up GEMM performance, and greatly improved High-Bandwidth Vector Memory (HVM) interface supporting outstanding requests and out-of-order responses. A high-performance HVM controller serving up to 16 cores and DMA accesses with 64 memory banks is optional for licensing. The AX46MPV now also includes BF16 full arithmetic mode as a standard feature. Additionally, the award-winning Andes Automated Custom Extension™ (ACE) is available in the 46-series, featuring customized vector instructions (ACE_RVV) with enhanced pipeline and Streaming Port (ASP).  

“We are thrilled to introduce the 3rd generation of the Andes Vector series, further strengthening our leadership in the AI SoC market,” said Dr. Charlie Su, President and CTO of Andes Technology. “Our NX27V and AX45MPV have been highly successful in high-performance AI SoC applications. The AX46MPV, boosted with both compute performance and memory bandwidth, is intended to bring the new-generation AI SoCs to the next level of compute density. Additionally, with enhanced capabilities in Linux, security, and AIoT, the highly configurable 46-series is a well-rounded solution with balanced performance, power, and area”

The AndesCore™ 46-series processor IP’s, 64-bit AX46MP(V) and 32-bit A46MP(V), can be configured from one core up to 16 cores. It is to be available for lead customers in Q1 2025 through the early access program and for general customers in Q2 2025. For further information about the Andes 46 series and Vector processors, please contact Andes Technology.

About Andes Technology

Nineteen years in business and a founding premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

Continue ReadingAndes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension
Read more about the article Andes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android

Andes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android

Hsinchu, Taiwan — Oct 18, 2024 — Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announces the AndesCore™ AX66 out-of-order superscalar multicore processor IP supporting the RVA23 profile. The AX66 is the 2nd member of the high-performance out-of-order AX60 series. Built on the success of the AX65 with the same 13-stage pipeline, 4-wide decode, and 8-wide out-of-order execution, the AX66 introduces many new features, including Vector and Vector Crypto support, Hypervisor and AIA, Multi-Cluster support with CHI, and RVA23 profile support. AX66’s versatile capabilities on performance scalability, multimedia, security, and virtualization makes it an ideal main processor in high-performance Linux and Android applications such as edge/data center AI, infotainment, networking, and vision/camera applications.

The AX66 boosts the SpecInt2006 performance over the 1st generation AX65 by more than 15%. Each core has 64KB private L1 instruction and data caches and up to 1MB private L2 cache, and each cluster contains up to 8 cores and a shared L3 cache up to 32MB. Besides the IO coherence interface already in the AX65, the AX66 adds a Coherence Hub Interface (CHI) for multi-cluster coherence. With the CHI interface support, we can use much more AX66 CPUs to work together in the same cache-coherent domain.  Together with the Hypervisor, AIA and optional IOMMU technologies, the AX66 can fully virtualize the entire multi-cluster CPU subsystem for resource sharing and security. Moreover, the AX66 supports the RISC-V standard external debug and instruction trace interfaces to facilitate fast system development, analysis and debugging.

“We are excited to announce our 2nd member of the top-of-the-line AX60 series, to further expand our portfolio,” said Dr. Charlie Su, President and CTO of Andes Technology. “We have added numerous features to the AX66, enabling its usage across a wide range of applications. With the RVV support, the AX66 can now handle more advanced AI/ML and multimedia applications. The inclusion of the Vector Crypto extension and the optional IOMMU provides the security capability for a modern day platform system. Additionally, the Hypervisor, AIA, CHI interface support make the AX66 suitable for the data center network applications such as Smart NIC or Data Processing Unit(DPU), and edge servers or devices running containerized applications. The inclusion of the RVA23 profile allows the AX66 to run Android OS on wearables, POS terminals, digital signage, and TV set-top boxes. We anticipate the AX66 to further penetrate high-end mainstream markets.”

The AndesCore™ AX66 is to be available for lead customers in Q4 2024 through the early access program and for general customers in 2025. For further information about the AX66 and the AX60 series processors, please contact Andes Technology.

 

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, automotive and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com . Follow Andes on LinkedIn, Twitter, Bilibili and YouTube!

Continue ReadingAndes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android
Read more about the article Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel

Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel

RISC-V: Shaping the Future of AI/ML, Application Processors, Automotive, and Security

San Jose, CA — Jun 6, 2024 — Andes Technology (TWSE: 6533), the leading vendor in high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, unveils its agenda of the annual ANDES RISC-V CON on June 11th at the San Jose Airport DoubleTree Hotel. This year’s theme, “ANDES RISC-V CON: Deep Dive into Automotive/AI/Application Processors and Security Trends,” promises an exhilarating journey into the RISC-V advancements. With over 300 registered attendees, this conference is set to be an industry luminary event, bringing together top-tier experts, researchers, and industry leaders for riveting discussions and groundbreaking insights.

The ANDES RISC-V CON boasts an exceptional lineup of presentations and two dynamic panels featuring key players in the RISC-V ecosystem. The AI panel, moderated by Dylan Patel, Chief Analyst at SemiAnalysis, includes Charlie Cheng from Andes Technology, Chris Walker from Untether AI, Jim Keller from Tenstorrent, and Raja Koduri from Mihira AI. This session will dive deep into “How Open-Source is Transforming AI and Hardware”. Another highlight is the Application Processing panel, moderated by Mark Himelstein, and with panelists consisting of Barna Ibrahim from RISE, Charlie Su from Andes Technology, Lars Bergstrom from Google, and Sandro Pinto from OSYX Technologies. This session will dive deep into how RISC-V eco-system aims at helping RISC-V processor to be used as application processor in a rich OS system, including Android and the others.

The event kicks off at 9:30 AM with a welcome address from Andes Technology’s Chairman and CEO, Frankwell Lin about the RISC-V market outlook, followed with a keynote by Dr. Charlie Su, President & CTO of Andes Technology, titled “Unlocking RISC-V’s Potential in Intelligent Application Processing.” From application processors to AI/ML accelerators, Dr. Su will first give an update on market adoption for RISC-V and show a couple examples of large-scale AI/ML SoCs adopting Andes AI/ML solutions. He will also explore the high-end processor usage scenarios. Marc Evans, Director of Business Development & Marketing at Andes, will discuss Andes’ automotive and security solutions. 

The exhibition will display a plethora of exciting RISC-V technologies, including the Andes Qilai testchip, a high-performance SoC with a quad-core RISC-V AX45MP cluster and an NX27V vector processor, designed to accelerate the development and porting of large RISC-V applications. Additionally, there will be an automotive-grade CMOS image sensor demo using the ISO 26262 fully-compliant AndesCore™ N25F-SE by MetaSilicon. Other demos featuring Andes RISC-V cores include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Canaan; the IT9836 TDDI demo board from ITE; the PC802SCB 5G small cell reference design from Picocom; and a Bluetooth development kit from Telink.

Additionally, renowned companies like Green Hills, IAR, Lauterbach, Piece Makers, RAIN AI, Siemens EDA, Synopsys (Imperas), and TetraMem will have speeches and booths. Alchip, Arteris, Menta, Rambus, RISE, RISC-V International, S2C, Sapeon, SHD, Signature IP, and Sondrel will have booths to engage and interact with attendees. 

ANDES RISC-V CON is the ultimate platform for RISC-V designers and developers to engage in meaningful dialogues with global experts. The conference will offer a stimulating and delightful experience, complete with a delicious lunch buffet and a relaxing evening reception. Stay until the end for a chance to win fabulous prizes including iPad in the Lucky Draw!

Best of all, this incredible event is free to attend! Don’t miss out on this extraordinary opportunity to be part of the RISC-V revolution. Register now and join the event for a day of innovation, inspiration, and networking!

👉 Register here: https://www.andestech.com/Andes_RISC-V_CON_2024_US/

 

About Andes Technology

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn, Twitter, Bilibili and YouTube! ! 

 

Continue ReadingAndes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel
Read more about the article Andes Technology Announced the QiLai SoC and the Voyager Development Board

Andes Technology Announced the QiLai SoC and the Voyager Development Board

May 30, 2024 – Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced the QiLai SoC and the Voyager development board to further accelerate the development and porting of large RISC-V applications.

The QiLai SoC chip includes high performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. The AndesCore™ AX45MP superscalar multicore contains a 2MB Level-2 cache, a coherence manager to manage Level-1 cache coherence, and a MMU (Memory Management Unit) for Linux based applications. The AndesCore™ NX27V vector processor with 512KB data cache supports a full range of RISC-V standard data types and Andes-enhanced data types optimized for AI workloads. The NX27V contains an efficient scalar unit and an out-of-order Vector Processing Unit (VPU) with 512-bit vector length (VLEN) and 512-bit data path width (DLEN), capable of generating up to 4 512-bit results per cycle. The NX27V can cooperate with the AX45MP cluster and make QiLai a heterogeneous software development platform where a Linux SMP system and an RTOS or bare-metal system can run simultaneously. The AX45MP and NX27V can run up to 2.2 GHz and 1.5GHz  respectively, and the total power consumption of the QiLai SoC is around 5W when running at its full speed.

The Voyager is a 9.6” x 9.6” Micro ATX form factor development board including a QiLai SoC, 16GB of DDR4 SIMM socket, JTAG debugger, USB to UART bridge, I2S Audio Codec, 16Mb SPI Flash for boot code, SD card socket, and several PCIe Gen4 slots that can bridge to many external devices such as GPU card and SSD. The supporting software includes the OpenSUSE Linux distribution, AndeSight™ toolchains, AndeSoft™ software stacks, and AndesAIRE™ NN SDK to convert AI/ML models to executables running on the NX27V vector processor.

“We are excited to announce the QiLai SoC which integrates our widely-adopted AndesCore™ AX45MP multicore and NX27V vector processor,” said Frankwell Lin, Andes Chairman and CEO. “These two processors have been licensed and silicon-proven by many customers though we are still pleased to see them working on our own silicon in the first cut. Manufactured at TSMC advanced 7nm process technology, the QiLai SoC and the Voyager development board demonstrate our commitment to enable the RISC-V software development in real time. Andes will keep its pure-play IP provider position, not going into chip business, this project is a response to provide better processor IP evaluation and application development purpose, and is an excellent resulting fruit from Andes GDR movement in 2021.”

“Andes has been asked by many partners and software developers for silicon-based platforms, where they can develop software for RISC-V more efficiently,” said Dr. Charlie Su, Andes President and CTO. “The Voyager board with the QiLai SoC is our response to that request and a great step towards enabling fast development and evaluation of a wide range of software for RISC-V, and further helps expand the RISC-V ecosystem.”

 

About Andes

Nineteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) and a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, functional safety and/or multi/many-core capabilities. By the end of 2023, the cumulative volume of Andes-Embedded™ SoCs has surpassed 14 billion.

For more information, please visit www.andestech.com or contact info@andestech.com

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