RISC-V CON Online is Coming!

RISC-V CON Series (English session, US)
RISC-V & SoC Architecture Exploration
for AI & ML Many-core Compute Arrays

Aug 27, Thursday ​
| English: 9:00 AM (PDT) |
Sep 1, Tuesday ​
| English: 9:00 AM (BST) |
Days
Hours
Minutes
Seconds

Subscribe to receive a weekly email notifying you about our latest  RISC-V CON online webinar events.

Upcoming Talks

All Talks

Topics Covered in RISC-V CON

- The powerful AndesCore™ V5, D25, 27-series, 45-series

- The cutting edge Andes RISC-V vector extension processor

- The leading solution Andes Custom Extension™

- The diverse AI applications of RISC-V

- The latest market trends and technology of RISC-V

RISC-V CON Webinar Series

8/27:
RISC-V & SoC Architecture Exploration for AI & ML Many-core Compute Arrays

Aug 27, Thursday
English:  9:00 AM (PDT) Register Now

Sep 1, Thursday
English:  9:00 AM (BST) Register Now

Speaker : 
John Min, Director of NA Field Application Engineering

Abstract: 
This presentation will describe the first RISC-V Processor with Vector extension implemented in TSMC 7nm FF+ process. It will describe the applications adopting RISC-V with demanding real-time and high performance computing as well as machine learning application. The solution to be shown in this presentation has a die area of 0.3mm 2 and high performance clock speed of 1 GHz.   

9/17:
An Introduction to RISC-V Vector Programming with C Intrinsic

Sep 17, Thursday
Chinese: 2:00 PM (GMT+8) Register Now
English:  5:00 PM (GMT+9) Register Now
English:  9:00 AM (PDT) Register Now

Speaker : 
Chih-Mao Chen, Advanced Engineer

Abstract: 
The "V" ISA extension for vector processing has been proposed to RISC-V to exploit data parallelism in domains such as machine learning and high-performance computing applications. In contrast to traditional SIMD processors with fixed-length vectors, the RISC-V vector extension defines a vector-length agnostic architecture where work is vectorized independently of a vector length that can be discovered at run-time. This is a departure from existing SIMD frameworks where the vector lengths are known statically, and a new intrinsic interface that takes advantage of scalable nature of RISC-V vectors is being developed by the community. This talk will provide an overview of the vector extension and how to program the vector processor, using Andes NX27V as an example, with C-level scalable vector types and intrinsic functions, as well as design choices and future evolution of the API.

3/12:
Andes RISC-V V5 CPUs

March 12, Thursday
 Chinese: 2:00 PM (GMT+8) 
 English:  4:00 PM (GMT+9)  
 English:  9:00 AM (PDT)  

Speaker : 
Chinese
Lai Yu-Fan, Technical Manager
English 
Tung Wei, Advanced Engineer

Abstract :
Introduction to Andes RISC-V CPU cores lineup, Andes Custom Extensions (ACE), software supports from bare metal to Linux, and Integrated Development Environment (IDE). People who join this webinar will learn what Andes could help designers to create highly competitive domain-specific SoCs easily.

3/26:
Andes Software Solutions for RISC-V

March 26, Thursday
 Chinese: 2:00 PM (GMT+8) 
 English:  4:00 PM (GMT+9)  
 English:  9:00 AM (PDT)  

Speaker : 
Chinese
Jimmy Shen, Senior Technical Manager
English 
Niraj Dengale, Advanced Engineer

Abstract :
AndeSight™ integrated development environment provides a friendly software development interface when developing SoC with AndesCore™ CPUs. In the past 15 years, with customer feedback and continuous product improvement, AndeSight™ has developed comprehensive functions. As for AndeSoft™ BSP, it provides a wealth of software projects under the command line, such as toolchain, bare metal demo programs, RTOS/Linux and DSP library related software.

4/9:
Andes Custom Extension™ - Accelerating Domain-Specific Architecture

 April 9, Thursday
 Chinese: 2:00 PM (GMT+8)  
 English:  4:00 PM (GMT+9)   
English:  9:00 AM (PDT)     

Speaker : 
YiChiang Chang, Technical Manager

Abstract :
With greatly increase the requirements for domain-specific application from edge to cloud, designers are looking for hardware acceleration methods to fulfill their specific requirements.  In this webinar, YiChiang will introduce Andes Custom Extension™ (ACE) to help Andes' customers convert the highly optimized Andes RISC-V V5 cores into domain-specific architecture to fulfill special acceleration.  He will also cover the major features of ACE and COPILOT, and share some practical examples for designers to accelerate their specific SW applications or algorithm by creating custom instructions through ACE.

4/23:
TWS (True Wireless Stereo) Solution Using Andes D25+ACE

April 23, Thursday
 Chinese: 2:00 PM (GMT+8)  
 English:  4:00 PM (GMT+9)   
English:  9:00 AM (PDT)   

Speaker : 
Tung Wei, Advanced Engineer

Abstract :
Andes D25, a power-efficient RISC-V CPU that supports P-extension for rich SIMD/DSP computation, is widely used in audio, voice, image and DSP applications. In addition, D25 is equipped with the powerful ACE (Andes Custom Extension™), which, by writing simple scripts and concise RTL codes, allows designers to new instructions to speed up critical functions and reduce power consumption at the same time.

TWS (True Wireless Stereo), a Bluetooth 5.0 technology, is expected to have continuous growth following leading vendors’ great success in their hot-selling TWS earphones. The challenge for SoC designers is to perform many complex computations fast and with low power consumption. In this webinar, we will introduce a unique solution for TWS based on D25 plus ACE acceleration. With the advantages of high flexibility, easy-to-integrate and low power, it perfectly addresses the requirements of TWS. It is the TWS solution you are looking for!

5/7:
Andes High Memory Efficiency 27 Series and Superscalar 45 Series CPU IP Cores

May 7, Thursday
 Chinese: 2:00 PM (GMT+8)  
 English:  4:00 PM (GMT+9)   
English:  9:00 AM (PDT)   

Speaker : 
Jason  Lin, Senior Technical Manager
KY Hsieh, Senior Technical Manager

Abstract :
Inheriting technologies from its successful 25-series, AndesCore™ 27-series is Andes Technology's second-generation RISC-V CPU IP solution. The recently released 32-bit A27 and 64-bit AX27 offer over 2 times higher bandwidth and deliver lower latency with its MemBoost technology, it is well suitable for memory-intensive applications, such as those run on Linux operating system.

The new 32/64-bit 45-series is an 8-stage in-order superscalar processor benefits from Andes’ proven 25-series cores, and compliant with the latest RISC-V specifications. It can issue two instructions per cycle and therefore significantly increases its performance. The superior pipelining results in world-class 5.4 Coremark/MHz, and can run up to 1.2GHz at 28nm in the worst case. The 45-series cores are ideal for embedded applications where response time and determinism are critical, such as 5G, AI, AR/VR, ADAS, IP surveillance, networking, storage, and V2X.
 
Join the webinar to learn the major features of 27 and 45 series processors!

5/21:
RISC-V Vector Extension and NX27V, the First Commercial RISC-V Vector Processor IP

May 21, Thursday
 Chinese: 2:00 PM (GMT+8)  
 English:  4:00 PM (GMT+9)   
English:  9:00 AM (PDT)   

Speaker : 
Chinese
Wilson Chi
, Deputy Director of Marketing Division
English
John Min,
Director of NA Field Application Engineering

Abstract:
The applications of AI, AR/VR, computer vision, cryptography, and multimedia require high-speed processing of large volumes of data. A RISC-V processor with the powerful RISC-V Vector (RVV) extension instruction set and parallel execution capability can significantly accelerate the performance of those applications.

AndesCore™ NX27V is the first commercial RISC-V processor to support RVV scalable vector instruction set, designed from ground up to be a Cray-like full vector computation machine. The NX27V provides a Vector Register File (VRF) with each register as large as 512 bits. Its supports RVV standard data types such as integer, fixed point, and floating point as well as Andes-enhanced data types optimized for AI representations. The NX27V contains a scalar unit and a Vector Processing Unit (VPU). The VPU has multiple functional units, operating on inputs of up to 512 bits each cycle in parallel to sustain the computational throughput needed in diversified applications. For software development support, in addition to the compilation tools and the performance simulator, Andes also provides a powerful visualization tool for the NX27V to help analyze and optimize the performance of critical computation kernels.

7/9:
Andes Infuses into
Artificial Intelligence:
High-Efficiency and High-Flexibility Processor IPs + NN SDK for AI

July 9, Thursday
Chinese: 2:00 PM (GMT+8)  
English:  5:00 PM (GMT+9)  
English:  9:00 AM (PDT)   

Speaker : 
Chinese
Simon Wang
, Technical Manager
English
John Min,
Director of NA Field Application Engineering

Abstract: 
To fulfill the diversity of AI applications (e.g., keyword spotting, object detection, etc.) in different environments including edge and cloud, Andes provides you with different choices to fit your AI targets with various requirements (computing power, power consumption, SRAM and code size). In this talk, Andes will introduce how RISC-V Packed-SIMD/DSP processors and RISC-V vector processors provide the high computing efficiency and flexibilities. Further with Andes NN SDK, it will be easy to integrate your AI applications to the shorter time-to-market, and achieve the outstanding utilization of hardware capabilities.

Close Menu