AndesCore™ N15(F), D15(F) Block Diagram
Hsinchu, Taiwan – December 6th, 2017 – Andes Technology Corporation (TWSE: 6533), the first Asia-based major supplier of innovative 32/64-bit processor IP cores and SoC design platform announced a series of 4 AndeStar™ V3-based high efficiency superscalar processors, the AndesCore™ N15/N15F/D15/D15F. The N15 implements integer baseline instructions while the D15 comes with DSP extension instructions; the N15F/D15F add a floating point unit (FPU) to the N15/D15. The series of processors is perfect for a wide range of applications such as sensors, smart meters, biometric, communication, audio/voice processing, image processing, medical devices, industrial applications, GPS, and drones.
The N15(F)/D15(F) are dual-issue processors capable of delivering performance at 5.41 CoreMark/MHz, the highest among similar products in the industry, with the max frequency of 500MHz at the 40LP process. The N15(F)/D15(F) come with various configuration options, including MMU for Linux OS and MPU for secure RTOSes. Instruction/data caches supports up to 64KB and instruction/data Local Memories up to 16MB respectively, all with optional ECC or parity support for overall SoC reliability. The 64-bit data paths for caches, Local Memories and the main bus provide the bandwidth needed for instruction fetch and data accesses to boost performance. The series of processors is designed for diversified performance-driven applications in the embedded Linux, Real-Time OS or bare metal environment.
The D15(F) with over 130 DSP and SIMD instructions, supported by C/C++ compiler and over 200 optimized DSP library functions, facilitates designers to focus on coding without resorting to assembly programming. The 8/16-bit SIMD instructions process four 8-bit and two 16-bit data in a single cycle, including two 16×16 multiplications, and considerably boost the performance of matrix computation, filter, Fourier transform and statistics calculation. The support of fixed-points, saturation, shift-and-round, and 64-bit operations offers developers all options to efficiently implement their algorithms with the desired precision while Zero-Overhead Loops (ZOL) eliminates the penalties of looping branches for tight loops. The N15(F)/D15(F) also include a built-in IEEE-754 compliant FPU which supports single-precision and double-precision floating-points.
Compared with similar superscalar processors in the industry, the N15(F)/D15(F) deliver 32% higher Dhrystones at 3.36 DMIPS/MHz, and feature 20% less area and 45% less power consumption under 28HPM process. In addition, the D15(F) is 97% faster than the competing processor in the function-equivalent DSP libraries and is also 48% faster in the FPU benchmarks.
“The N15(F)/D15(F) series are versatile processors designed based on a 6-stage asymmetrical dual-issue pipeline micro-architecture, where 2 pipelines are not identical,” said Dr. Charlie Su, CTO and Senior VP of R&D of Andes Technology. “The asymmetrical structure leads to less hardware resources and lower power consumption while still capable of delivering superior performance with the highly-optimized compiler as witnessed by the leading results of integer, DSP and FPU benchmarks. They can perform a pair of loads in parallel, complete a 32×32 multiplication in one cycle, and support a fast radix-4 divider, with dynamic branch predication to further boost overall performance. The N15(F)/D15(F) include debug module and trace support as well as the StackSafe™ stack protection to help catch tough bugs. In addition, the N15(F)/D15(F) offer standby control, PowerBrake power throttling, and automatic suspend-to-RAM control to meet different power management requirements.”
“By combining superior superscalar hardware architecture performance, built-in FPU, optimized compiler and efficient DSP library, the N15(F)/D15(F) meet the needs of a wide variety of applications and allow customers to shorten development time and deliver competitive products easily. The D15(F) has been licensed for customers to design in their multimedia chips.“
