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AndesCore™ D45-SE
AndesCore™ D45-SE Overview
- 32-bit in-order dual-issue 8-stage pipeline CPU architecture
- AndeStar™ V5 Instruction Set Architecture (ISA)
- Compliant to RISC-V RV32 GCBP little endian:
- RV-GC: Integer, single/double precision floating point and 16-bit extensions
- RV-B Bit manipulation extensions
- RV-P (draft) DSP/SIMD extensions
- Andes V5 performance/code size extensions
- 16/32-bit mixable instruction format for compacting code density
- Advanced low power branch predication to speed up control code
- Return Address Stack (RAS) to accelerate procedure returns
- Physical Memory Protection(PMP), and programmable Physical Memory Attribute (PMA)
- MemBoost for heavy memory transactions
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to reduce program code size
The 32-bit D45-SE is an 8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level functional safety for automotive applications. Approved based on the functional safety assignments of a Safety Element Out-of-Context (SEooC), which includes the ISO 26262 compliant development process and the qualitative approach with respect to hardware safety analysis, D45-SE is certified to be used in safety-related applications such as Millimeter Wave Radar Sensor, Around View Monitor system (AVMS), Vehicle Instrument Cluster, Powertrain DCU, Infotainment DCU, Front/Rear different applications for ZCU.
The D45-SE includes “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructions, and “B” bit manipulation. D45-SE equipped with comprehensive SIMD/DSP instructions that can boost the performance of voice, audio, image and signal processing. Its ”B” extensions provide some combination of code size reduction, performance improvement, and energy reduction, and “FD” extensions support IEEE754-compliance single and double precision floating point instructions. D45-SE incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. Other features include ECC for memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™ and StackSafe™ for software quality improvement, PowerBrake and WFI for power management.
Applications
- Supports a wide range of applications from ASIL B to ASIL D, including Millimeter Wave Radar Sensor, Around View Monitor system (AVMS), Vehicle Instrument Cluster, Powertrain DCU, Infotainment DCU, Front/Rear different applications for ZCU.
- Compliant with ISO 26262:2018 standard parts 2, 4, 5, 7, 8 and 9 for ASIL-D
- Independent assessment and certification by SGS-TÜV Saar GmbH
- AndesCore™ D45-SE ISO 26262 compliant certificate (need to add diagram connection)
Development Tools
- AndeSight™ Integrated Development Environment
- ICE debugging hardware
Key Features and Performance
ISO 26262 Functional Safety
Key Features | Benefits |
---|---|
Certified according to ISO 26262:2018 edition series of standards | Compliant with the latest version of standards |
Andes Technology Development Process certified by parts 2, 4, 5, 6, 8 and 9 of the standards for components up to ASIL D | To prevent systematic failures |
AndesCore™ D45-SE CPU IP certified by parts 2, 4, 5, 7, 8 and 9 of the standards in compliance with ASIL D requirements. Auxiliary document (Application Note) to help licensee to pass ASIL-B. | To prevent random hardware failures |
Supporting internal and external safety mechanisms; including qualitative DFMEA (Design Failure Mode and Effects Analysis) and quantitative FMEDA (Failure Modes, Effects, and Diagnostic Analysis) evaluations | Facilitate functional safety product integration and certification |
Certified by SGS-TÜV Saar GmbH, with DAkkS logo | Audited independently by credible third-party certification body |
AndeStar™ V5 Architecture
Key Features | Benefits |
---|---|
RISC-V RV32GCPB ISA |
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Andes Extended Instructions | Andes exclusive performance and functionality enhancements |
16/32-bit mixable instruction format | For compact code density |
32 general-purpose registers | For better code size and performance |
Machine (M), User (U) and Supervisor (S) Privilege levels | For Linux and advanced operating systems with protection between kernel and user programs |
CPU Core
Key Features | Benefits |
---|---|
6.12 Coremark/MHz, 2.96 DMIPS/MHz* | Excellent performance-per-MHz |
8-stage dual-issue in-order pipeline | Superior performance-efficiency, while allowing for high speeds |
Extensive branch predication features
|
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Physical Memory Protection (PMP), configurable up to 32 regions | Basic read/write/execute memory protection with minimum cost |
Programmable Physical Memory Attribute (PMA), configurable up to 16 regions | Configurable memory attributes:
|
Performance monitors | Program code performance tuning |
Multiplier options
| Option to choose between speed and area according to application's requirements |
PowerBrake technology | Performance throttling to digitally reduce power consumption |
StackSafe™ hardware stack protection |
|
QuickNap™ technology | Fast power-down/wake-up support for caches |
* BSP v5.1.0, DMIPS/MHZ follow Dhrystone’s no-inline ground rules, best performances
Memory Subsystems
Key Features | Benefits |
---|---|
I-Cache & D-Cache
|
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ILM & DLM
|
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MemBoost | Optimize cache reads and writes to achieve higher bandwidth and lower latency |
Soft-error protection: parity for I-Cache, and ECC for D-Cache, ILM and DLM | Code and data integrity protection |
Bus master port: AXI with 64/128-bit data | User-selectable bus interface for optimal efficiency |
Bus save port: AXI with 64/128-bit data, for ILM/DLM accesses | Efficient data transfer between CPU and SoC masters |
Core/bus clock ratio of N:1 | Simplified SoC integration |
64-bit AXI Peripheral Port Interface | For latecny-sensitve peripheral |
Platform-Level Interrupt Controller (PLIC)
Key Features | Benefits |
---|---|
Implements RISC-V PLIC specification
| Allow individual interrupts to be serviced and prioritized without sharing |
Enhanced interrupt features
|
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Debug Support
Key Features | Benefits |
---|---|
Implements RISC-V debug specifications ver 0.13 | Supported by industry debug tool suppliers |
JTAG Debug Port | Industry-standard support |
Embedded Debug Module with up to 8 triggers | Flexible configurations to tradeoff between gate count and debugging capabilities |
Exception redirection support | Entering debugger upon selected exceptions without using breakpoints |
Trace Support
Key Features | Benefits |
---|---|
Implements RISC-V Trace 1.0 Instruction Trace interface | Supported by Andes tools |
Product Package
AndesCore™ D45-SE Single-core Processor with AE350 AXI Platform
- Pre-integrated D45-SE single-core CPU subsystem, PLIC, Debug Module, and AXI Platform
- D45-SE processor core certified for functional safety usage
- Safety package for safety developments
- AE350 platform for design reference