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AndesCore™ AX65
Superscalar Out-of-Order Execution Multicore Cluster
AndesCore™ AX65 Overview
- 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
- Symmetric multiprocessing up to 8 cores
- Level-2 cache and coherence support
- AndeStar™ V5 Instruction Set Architecture (ISA)
- Compliant to RISC-V GCB, scalar cryptography and CMO extensions
- RVA22 profile compliant
- 64-bit architecture for memory space over 4GB
- TAGE Branch predication for highly accurate prediction
- Linux-capable Memory Management Unit (MMU)
- Physical Memory Protection (PMP) and latest architecture enhancement extension (ePMP) for access permission controls
- Andes-enhanced Platform-Level Interrupt Controller (PLIC) for a wide range of system events and real-time performance
- ECC or Parity for SRAM error protection
- PowerBrake and WFI (Wait for Interrupt) for different power saving occasions
AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMA-FD)”, “C” 16-bit compression, “B” bit manipulation, “K” (scalar crypto), CMO extensions, and Andes performance enhancements. It features MMU for Linux based applications, TAGE branch prediction for accurate branch execution, 4 wide instruction decode, 8 independent functional pipelines (4 integer, 2 fp, 2 load/store), level-1 instruction/data caches for low-latency accesses. The AX65 symmetric multiprocessor supports up to eight cores and a level-2 cache controller with instruction and data prefetch. Coherence Manger ensures data coherence among CPU accesses and IO transactions from cacheless bus managers. Other features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, and PowerBrake and WFI for power management.
Development Tools
- AndeSight™ Integrated Development Environment (Eclipse-based)
- AndeShape™ FPGA Development Boards
Key Features and Performance
AndeStar™ V5 Architecture
Key Features | Benefits |
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RISC-V RV64 GCB + scalar cryptography + CMO |
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Andes Extended Instructions | Andes exclusive performance and functionality enhancements |
MMU and Sv39/Sv48 virtual memory translation | For Linux and advanced operating systems with protection between kernel and user program |
64-bit CPU architecture | Enabling software to utilize the memory spaces far beyond the 4G byte limit of 32-bit CPUs |
Machine (M), optional User (U) and Supervisor (S) Privilege levels | privilege protections |
CPU Core
Key Features | Benefits |
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9.25 CoreMark/MHz, 4.9 DMIPS/MHz, 8.25 specint2006/Ghz | Superior performance |
13-stage out-of-order 4 wide superscalar pipeline | Superior performance-efficiency, while allowing for high speeds |
Extensive branch predication features
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Physical Memory Protection (PMP), configurable up to 16 regions | Basic read/write/execute memory protection with minimum cost |
16 programmable physical memory attributes (PPMA) regions | Configurable memory attributes:
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Performance monitors | Program code performance tuning |
PowerBrake technology | Performance throttling to digitally reduce power consumption |
Memory Subsystems
Key Features | Benefits |
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Level-1 I-Cache & D-Cache
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Level-2 I/D Unified Cache
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Optional ECC error protection with SRAM interface | Code and data integrity protection |
Bus manager port: AXI with 256 bit data, I/D joint or separate bus | High throughput with wide data path |
Core/bus clock ratio of N:1 | Simplified SoC integration |
Multicore Cache Coherence
Key Features | Benefits |
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Platform-Level Interrupt Controller (PLIC)
Key Features | Benefits |
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Implements RISC-V PLIC specification
| Interrupt handling for SoC with multiple processors |
Enhanced interrupt features
| Complete hardware preemption support |
Debug Support
Key Features | Benefits |
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Implements RISC-V debug specification v1.0 | Supported by industry debug tool suppliers |
JTAG Debug Port | Industry-standard support |
Embedded Debug Module with up to 8 triggers | Flexible configurations to tradeoff between gate count and debugging capabilities |
Exception redirection support | Entering debugger upon selected exceptions without using breakpoints |
RISC-V Trace 1.0 Instruction Trace interface | Supported by Andes tools |