AndesCore™ AX66
RVA23, Multi-cluster, Hypervisor and Android
AndesCore™ AX66 Overview (Preliminary)
- 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
- Symmetric multiprocessing up to 8 cores
- Private L2 cache support
- Level-3 shared cache and coherence support
- AndeStar™ V5 Instruction Set Architecture (ISA)
- Compliant to RISC-V GCBV and Vector Cryptography
- Hypervisor(RVH)
- RVA23 profile compliant
- 64-bit architecture for memory space over 4GB
- TAGE Branch predication for highly accurate prediction
- Linux-capable Memory Management Unit (MMU)
- Physical Memory Protection (PMP) and latest architecture enhancement extension (ePMP) for access permission controls
- AIA with APLIC and IMSIC support
- ECC or Parity for SRAM error protection
- StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
- PowerBrake and WFI (Wait for Interrupt) for different power saving occasions
AndesCore™ AX66 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMA-FD)”, “C” 16-bit compression, “B” bit manipulation, Vector and Vector Cryptography, Hypervisor and AIA, and Andes performance enhancements. It features MMU for Linux based applications, TAGE branch prediction for accurate branch execution, 4 wide instruction decode, 8 independent functional pipelines (4 integer, 2 Fp/Vector, 2 load/store), level-1 instruction/data caches and private level-2 cache for low-latency accesses. The AX66 symmetric multiprocessor supports up to eight cores and a level-3 cache controller with instruction and data prefetch. Coherence Manger ensures data coherence among CPU accesses and IO transactions from cacheless bus masters. Other features include ECC for cache memory soft error protection, CHI interface for cache coherent multi-cluster, StackSafe™, and PowerBrake and WFI for power management.
Applications
- Networking and Communications
- Android Devices
- Video and Multimedia Processing
- SmartNIC or DPU
- AI SoC
- Edge Servers
Block Diagram
Development Tools
- AndeSight™ Integrated Development Environment (Eclipse-based)
- AndeShape™ FPGA Development Boards
Key Features and Performance
AndeStar™ V5 Architecture
| Key Features | Benefits |
|---|---|
| RISC-V RV64 GCB + Vector/Vector Crypto, Hypervisor/AIA |
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| Andes Extended Instructions | Andes exclusive performance and functionality enhancements |
| MMU and Sv39/Sv48 virtual memory translation | For Linux and advanced operating systems with protection between kernel and user program |
| 64-bit CPU architecture | Enabling software to utilize the memory spaces far beyond the 4G byte limit of 32-bit CPUs |
| Full privilege protections with or without hypervisor |
CPU Core
| Key Features | Benefits |
|---|---|
| >9.5 specint2006/Ghz (estimated) | Superior performance |
| 13-stage out-of-order 4 wide superscalar pipeline | Superior performance-efficiency, while allowing for high speeds |
Extensive branch predication features
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MMU (Memory Management Unit):
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| Physical Memory Protection (PMP), configurable up to 16 regions | Basic read/write/execute memory protection with minimum cost |
| 16 programmable physical memory attributes (PPMA) regions | Configurable memory attributes:
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RISC-V Vector support with 128bit VLEN
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| Performance monitors | Program code performance tuning |
| StackSafe™ hardware stack protection | Easy identification of stack size threshold during development Hardware error detection of stack overflow and underflow at runtime |
| PowerBrake technology | Performance throttling to digitally reduce power consumption |
Memory Subsystems
| Key Features | Benefits |
|---|---|
Level-1 I-Cache & D-Cache
Private Level-2 I/D Unified Cache
Shared Level-3 cache
| Accelerating accesses to slow memories Further accelerate performance with optional larger 2nd level private cache Larger 3rd level share cache |
| Optional ECC error protection with SRAM interface | Code and data integrity protection |
| Bus manager port: AXI with 128 or 256 bit data, I/D joint or separate bus | High throughput with wide data path |
| Core/bus clock ratio of N:1 | Simplified SoC integration |
Multicore Cache Coherence
| Key Features | Benefits |
|---|---|
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Advanced Interrupt Architecture (AIA)
| Key Features | Benefits |
|---|---|
Implements RISC-V AIA specification v1.0 |
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Debug Support
| Key Features | Benefits |
|---|---|
| Implements RISC-V debug specification v1.0 | Supported by industry debug tool suppliers |
| JTAG Debug Port | Industry-standard support |
| Embedded Debug Module with up to 8 triggers | Flexible configurations to tradeoff between gate count and debugging capabilities |
| Exception redirection support | Entering debugger upon selected exceptions without using breakpoints |
| RISC-V Trace 1.0 Instruction Trace interface | Supported by Andes tools |