AndesCore™ AX45MPV

• 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
• Symmetric multiprocessing up to 8 cores
• Level-2 cache and coherence support
• AndeStar™ V5 Instruction Set Architecture (ISA)
  • Compliant to RISC-V GCBPV extensions
  • Andes performance extension
  • Andes CoDense™ extension for further compaction of code size
• Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
• 64-bit architecture for memory space over 4GB
• Branch predication to speed up control code
• Linux-capable Memory Management Unit (MMU)
• Physical Memory Protection (PMP) and programmable Physical Memory Attribute (PPMA)
  • Andes-enhanced Platform-Level Interrupt Controller (PLIC) for a wide range of system events and real-time performance
• Multiprocessing up to 8 cores with hardware managed data coherence
• Configurable VPU vector length (VLEN) and datapath length (DLEN)
• Easy arrangement of preemptive interrupts
• ECC or Parity for SRAM error protection
• StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
• Versatile configurations to tradeoff between core size and performance requirements
• PowerBrake and WFI (Wait For Interrupt) for different power saving occasions

AndesCore™ AX45MPV 64-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture. It supports RISC-V standard “G (IMA-FD)”, “C” 16-bit compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector) extensions, and Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions. It features MMU for Linux based applications, dynamic branch prediction for efficient branch execution, dual-issue of common instruction pairs, level-1 instruction/data caches and local memories for low-latency accesses. The AX45MPV symmetric multiprocessor supports up to eight cores and a level-2 cache controller with instruction and data prefetch. Coherence Manger ensures data coherence among CPU accesses and IO transactions from cache less bus masters. The AX45MPV contains a powerful VPU with up to 1024-bit VLEN and DLEN, and is excellent for computations involving large arrays of data such as computer vision, cryptography, image processing, machine/deep learning, and scientific computing. Other features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™, StackSafe™ for software quality improvement, PowerBrake and WFI for power management.