AndesCore™ A27L2 Overview
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- Floating point extensions
- DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
- Andes extensions, architected for performance and functionality enhancements
- Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
- 32-bit, 5-stage pipeline CPU architecture
- 16/32-bit mixable instruction format for compacting code density
- Branch prediction to speed up control code
- Return Address Stack (RAS) to speed up procedure returns
- Memory Management Unit (MMU), Physical Memory Protection (PMP) and Programmable Physical Memory Attributes (PMA)
- Level-1 and level-2 cache controllers with 64-byte cache line size
- MemBoost for heavy memory transactions
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to further reduce code size on top of “C” extension
The 32-bit A27L2 is a 5-stage processor that supports the latest RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructions, “N” for user-level interrupts, and Memory Management Unit (MMU) for Linux support.
A27L2 features branch prediction, level-1 instruction and data caches, level-2 unified cache, local memories, ECC error protection, and Andes Custom Extension™ to add custom instructions to accelerate performance and reduce power consumption. In addition, it incorporates MemBoost to greatly enhance memory bandwidth and reduce memory latencies for applications with intensive memory accesses. A27L2 also includes vectored and preemptive interrupt controller to serve diversified system events, AXI 128-bit bus, rich power management, and JTAG debug interface and trace interface for software development support.
Development Tools
- AndeSight™ Integrated Development Environment
- COPILOT: Custom-OPtimized Instruction deveLOpment Tool for ACE
- ICE debugging hardware
Key Features and Performance
AndeStar™ V5 Architecture
Key Features | Benefits |
---|---|
RISC-V RV32GCPN ISA |
|
RISC-V P-extension (draft) DSP/SIMD instructions with versatile operations | Boost the performance of voice, audio, image and signal processing |
RISC-V single and double precision floating point instruction | Accelerate the processing of high precision arithmetic |
Andes Extended Instructions | Andes exclusive performance and functionality enhancements |
Andes Custom Extension™ (ACE) option to create customized instructions for software acceleration |
|
16/32-bit mixable instruction format | For compact code density |
32 general-purpose registers | For better code size and performance |
Machine (M), User (U) and Supervisor (S) Privilege levels | For Linux and advanced operating systems with protection between kernel and user programs |
CPU Core
Key Features | Benefits |
---|---|
3.57 Coremark/MHz, 1.98 DMIPS/MHz* | Superior performance-per-MHz |
5-stage pipeline, with a full-cycle reserved for critical SRAM accesses | Superior performance-efficiency, while allowing for high speeds |
Extensive branch prediction features
|
|
Memory Management Unit
|
|
Physical Memory Protection (PMP), 16 regions | Basic read/write/execute memory protection with minimum cost |
Programmable Physical Memory Attribute (PMA), 16 regions | Configurable memory attributes:
|
Performance monitors | Program code performance tuning |
StackSafe™ hardware stack protection |
|
Multiplier options
| Option to choose between speed and area according to application's requirements |
PowerBrake technology | Performance throttling to digitally reduce power consumption |
QuickNap™ technology | Fast power-down/wake-up support for caches |
* AndeSight v500, DMIPS/MHZ follow Dhrystone’s no-inline ground rules, best performances
Memory Subsystems
Key Features | Benefits |
---|---|
Level-1 I-Cache & D-Cache
|
|
Level-2 I/D Unified Cache
|
|
ILM & DLM
|
|
MemBoost – Data Cache Write-Around | Smart cache line allocation policy, for better cache utilization and reduce number of memory accesses |
MemBoost – Instruction and Data Pre-fetch | Conditionally fill instruction and data caches in advance, for minimum memory access latency |
MemBoost – Multiple Outstanding Mem. Req. | Issue multiple transactions to data memory sub-system for higher bus utilization, also support out-of-order completion |
Soft-error protection: ECC or parity for I-Cache and D-Cache, ILM and DLM with SRAM interface | Code and data integrity protection |
Bus manager port: AXI with 128-bit data bus | High throughput with wide data path |
Bus subordinate port: AHB with 128-bit data, for ILM/DLM accesses | Efficient data transfer between CPU and SoC managers |
Core/bus clock ratio of N:1 | Simplified SoC integration |
Platform-Level Interrupt Controller (PLIC)
Key Features | Benefits |
---|---|
Implements RISC-V PLIC specification
| Allow individual interrupts to be serviced and prioritized without sharing |
Enhanced interrupt features
|
|
Debug Support
Key Features | Benefits |
---|---|
Implements RISC-V debug specifications | Supported by industry debug tool suppliers |
JTAG Debug Port | Industry-standard support |
Embedded Debug Module with up to 8 triggers | Flexible configurations to tradeoff between gate count and debugging capabilities |
Exception redirection support | Entering debugger upon selected exceptions without using breakpoints |
Performance
Core, Process | A27L2, 28nm |
---|---|
Frequency (MHz) | 1000 |
Dynamic power (uW/MHz) | 28 |
Area (mm2) | 0.256 |
* Configured with 32KB L1 instruction and data caches, 256KB L2 cache, MMU with 256-entry BTB, 16-entry PMP and 16-entry PMA, without DSP and FPU. Using SVT 9-track library, SS corner, 0.81V, -40°C, and with I/O constraint. Power consumption at TT corner, 0.9V, 25°C
Product Package
AndesCore™ A27L2 Single-Core Processor with AE350 Platform
- Pre-integrated A27L2 with CPU subsystem (including PLIC, Timer and Debug Module), and AXI platform