AndesCore™ NX25 Overview

  • AndeStar™ V5 64-bit Instruction Set Architecture
  • RISC-V compliance plus Andes performance enhancement extensions
  • Dynamic branch prediction to accelerate complex programs
  • Individually configurable caches and Local Memories for instruction and data
  • Native support of AXI/AHB bus master and AHB bus slave ports
  • Platform-Level Interrupt Controller (PLIC) enhanced with vectored interrupt dispatch
  • Fast and compact design to reach over 1 GHz at 28nm
  • Product packages of NX25 with CPU Subsystem, and NX25 with AHB Platform

The AndesCore™ NX25 is a CPU IP core based on the 64-bit version of AndeStar™ V5 Instruction Set Architecture, which supports the popular RISC-V technology from the latest development in computer architecture and is boosted by Andes' performance enhancement such as StackSafe™, PowerBrake and vectored interrupt controller. The 64-bit NX25 is capable of addressing applications with memory usage greater than 4G bytes. Designed with a fast and compact 5-stage pipeline, the NX25 reserves one full cycle for critical SRAM accesses to better match the speed of pipeline logic at advanced process nodes and reach over 1 GHz at 28nm. Configurations for performance-power-area trade-offs include high speed or small gate count multiplier, optional dynamic branch prediction with Branch Target Buffer, Branch History Table and Return Address Stack, and choices of Local Memories and/or caches. Additional features for the NX25 include 64-bit AXI or AHB bus master port, 64-bit AHB slave port for Local Memory accesses, the enhanced Platform-Level Interrupt Controller (PLIC), and exception redirection that automatically triggers debugging events.

Applications

  • Large-scale network controllers
  • High capacity storage devices
  • Data analytic accelerators
  • Computer Vision and Pattern Recognition
  • Artificial Intelligence to Deep Learning

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment
  • ICE debugger hardware

Key Features and Performance

AndeStar™ V5 Architecture
Key Features Benefits
RISC-V RV64IMAC Instructions
  • State-of-the art ISA from latest developments in computer architecture
  • Industry standard and open architecture
64-bit CPU architecture Enabling software to utilize the memory spaces far beyond the 4G byte limit of 32-bit CPUs
Andes Extended Instructions Instructions to enhance performance and code size
16/32-bit mixable instruction format For compact code density
32 general-purpose registers For better code size and performance
Machine (M) and User (U) Privilege levels Embedded systems with privilege protections
CPU Core
Key Features Benefits
3.20 DMIPS/MHz* 3.45 CoreMark/MHz* Superior performance per-MHz
5-stage pipeline, with a full-cycle reserved for critical SRAM accesses Superior performance-efficiency, while allowing for high speeds
Extensive branch predication features
  • Branch Target Buffer (BTB): 32, 64, 128 or 256-entry
  • Branch History Table (BHT): 256-entry, with 8-bit branch history
  • Return Address Stack (RAS): 4-entry
  • Branch Target Buffer and Branch History Table to speed up control codes
  • Return Address Stack to speeds up procedure returns
StackSafe™ hardware stack protection
  • Easy identification of stack size threshold during development
  • Hardware error detection of stack overflow and underflow at runtime
Multiplier options
  • Fast multiplier: pipelined, 2-cycle
  • Small multipliers: producing 1, 2, 4, or 8 bits per cycle
Option to choose between speed and area according to application's requirements
PowerBrake technology Performance throttling to digitally reduce power consumption

* AndeSight v3.1.0

Memory Subsystems
Key Features Benefits
I-Cache & D-Cache
  • Size: 8KB to 64KB
  • Set associativity: Direct-mapped, 2-way or 4-way
  • Accelerating accesses to slow memories
  • Flexible cache configurations
ILM & DLM
  • Size: 4KB to 16M
  • SRAM or AHB-Lite interface support
  • Bus masters accesses by AHB slave port
  • For deterministic and efficient program execution
  • Flexible size selection to fit diversified needs
Soft-error protection: ECC or parity for I-Cache and D-Cache, ILM and DLM with SRAM interface Code and data integrity protection
Bus master port: AHB or AXI with 64-bit data, 32 to 64-bit address User-selectable bus interface for optimal efficiency
Bus save port: AHB with 64-bit data, for ILM/DLM accesses Efficient data transfer between CPU and SoC masters
Core/bus clock ratio of N:1 Simplified SoC integration
Platform-Level Interrupt Controller (PLIC)
Key Features Benefits
Implements RISC-V PLIC specification
  • Up to 1023 PLIC interrupt sources
  • Up to 255 PLIC interrupt priority levels
  • Up to 16 PLIC interrupt targets
Allow individual interrupts to be serviced and prioritized without sharing
Enhanced interrupt features
  • Vectored interrupt dispatch
  • Priority-based preemption
  • Selectable edge trigger or level trigger
  • Faster interrupt handling for real-time applications
  • Complete hardware preemption support for faster response
  • Flexible interrupt source interface for simpler SoC design
Debug Support
Key Features Benefits
Implements RISC-V debug specifications Supported by industry debug tool suppliers
5-wire JTAG Debug Port Industry-standard 5-wire support
Embedded Debug Module with up to 8 triggers Flexible configurations to tradeoff between gate count and debugging capabilities
Exception redirection support Entering debugger upon selected exceptions without using breakpoints
Performance
Process 28HPC
Frequency (MHz) 50
Dynamic power (uW/MHz) 11
Area (mm2) 0.04

Process 28HPC
Frequency (MHz) 1000
Dynamic power (uW/MHz) 16
Area (mm2) 0.05

Base configuration, RVt 12-track library, SS corner, 0.81V, 0°C, and with I/O constraint. Power consumption at typical process corner, 0.9V, 25°C



Product Packages

NX25 with CPU Subsystem

  • Pre-integrated NX25, PLIC, Debug Module and simulation-only encrypted AHB Platform

NX25 with AHB Platform

  • NX25 with CPU Subsystem, plus AHB Platform