AndesCore™ N10 Overview

  • Caches for fast code and data accesses
  • Local Memories for deterministic code and data accesses
  • IEEE754-compliant FPU coprocessor
  • Memory Protection Unit (MPU) for secure RTOS
  • Memory Management Unit (MMU) for Linux

The mid-range Andes Technology N10 processor is ideal for applications ranging from consumer media players and smart glasses all the way to touch panel processing, motor control, and power management. The N10 features a 5-stage pipeline and operates at over 800 MHz clock rate providing plenty of performance for automotive electronics and industrial control. It also comes with I/D cache or local memory options that enable the core to more efficiently perform for networking or communication applications.

In the fast growing IoT market, the highly performance efficient N10 processor can be used as IoT gateway to bridge those ZigBee, Bluetooth or WiFi sensor devices to the internet connectivity. In addition, with the tightly-coupled IEEE-754 compliant NCESFP100 single-precision floating point unit (FPU), the N10 processor can be used in the high precision sensor devices to manipulate the data from ADC which converts physical continuous sensor signals to digital data.

Applications

  • Video event data recorder (VEDR)
  • Wireless device
  • Networking device
  • Storage device
  • DSC
  • DVC
  • Digital home
  • Embedded controller

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment
  • AICE JTAG/SDP debugger hardware

Key Features and Performance

AndeStar™ V3 Architecture
Key Features Benefits
21st-century RISC instruction set Better performance for modern compiler
16/32-bit mixable opcode format Smaller code size
Optional saturation instructions Efficient voice applications
16 or 32 general-purpose registers Trade-off between core size and performance requirements
All-C Embedded Programming Faster SW development and easier maintenance
Shadow stack pointer Efficiency and protection with a dedicated kernel stack pointer
Hardware divider More performance
Aligned and unaligned load/store multiple word instructions and post-increment load/store memory accesses Better program code size and performance
Direct support of up to 32 interrupts with programmable priority levels Quick identification of interrupt sources and fast assignment of service routines
4G address space Full range address space
Memory mapped IO Friendliness to programmers and compilers
CPU Core
Key Features Benefits
2.41 DMIPS/MHz*
3.90 CoreMark/MHz*
Superior performance-per-MHz
5-stage pipeline Superior performance-efficiency, while allowing for high speeds
Extensive branch predication (BTB and RAS) Better performance for branches
Hardware stack protection Stack size determination and runtime overflow error detection
Processor state bus Simplification SoC design and debugging
Performance monitors Program code performance tuning
Memory Management Unit
  • 32/64/128-entry 4-way set-associative main TLB
  • Hardware page table walker
  • Support two groups of page size (4KB & 1MB, 8KB & 1MB)
  • Virtual memory support for full address space and easy code/data sharing
  • Support for full-featured OS such as Linux
  • Protection of superuser and user privilege
  • Hardware for fast address translation
Memory Protection Unit
  • 8 memory protection regions
Basic read/write/execute memory protection with minimum cost
Choice of multipliers
  • Fast for performance
  • Small for size
Application specific configurations
  • More performance
  • Smaller size
Extensive clock gating and logic gating Lower power
N:1 core/bus clock ratios Simplified SoC integration
Low-latency vectored interrupt Faster context switch for real-time applications
Completion of most operations in 1 cycle Single-cycle capable for Local Memory and AHB bus accesses Better performance-efficiency
PowerBrake technology Peak power consumption reduction
Coprocessor interface For Andes FPU and other customer designed coprocessor unit

* Toolchain BSP v 4.1.0

Memory Subsystems
Key Features Benefits
I & D Cache
  • Virtually Indexed and Physically Tagged (VIPT)
  • Size:4KB to 64KB, line size:16B/32B
  • Set associativity: Direct-mapped/ 2 Way
Higher performance for large program size
  • Accelerating accesses to slow memories
  • Flexible cache configurations
  • VIPT for low power on context switch
Optional External Instruction and Data Local Memory
  • Size: 0KB to 4MB
  • ILM: program code, data and IO
  • DLM: program data
Higher efficiency for program execution
  • Flexible size selection to fit diversified needs
Optional 2D local memory DMA Efficient data transfer
BIU supports 32-bit AHB/2AHB/AHB-lite/APB or 32-bit/64-bit AXI User-selectable bus interface for optimal efficiency
Debug Support
Key Features Benefits
2-wire Serial Debug Port or 5-wire JTAG Debug Port Low-cost 2 wire support and industry-standard 5-wire support
Embedded Debug Module (EDM)
  • Up to 8 breakpoints and watchpoints
  • Secured debug access to system address space
  • Flexible configurations to trade off gate count and debugging capabilities
  • Code and data protection by allowing only authorized debugging
Performance
Process 90LP 40LP 28HPM
Frequency (MHz) 50 50 50
Dynamic power (uW/MHz) 32.0 13.3 7.9
Area (mm2) 0.17 0.059 0.030

* Base configuration, RVt library. ; Power consumption at typical process corner, Vdd (90LP: 1.2V, 40LP:1.1V, 28HPM: 0.9V), 25°C

Process 40LP 28HPM
Max frequency (MHz) 623 1000
Dynamic power (uW/MHz) 9.2 8..1
Area (mm2) 0.093 0.050

* Base configuration, LVt library; Frequency at slow process corner, 40LP: 0.99V, 28HPM:0.81V, 125°C and without I/O constraint; Power consumption at typical process corner, Vdd (40LP:1.1V, 28HPM: 0.9V) , 25°C