AndesCore™ N8 Overview

  • Excellent total performance deliverable
  • Vectored interrupt for low latency interrupt processing
  • Small footprint with low gate count and high code density
  • Speed-up and power reduction for Flash accesses by FlashFetch technology

System-on-chip designs are proliferating to help OEMs automate functions such as smart lights, heating and cooling, wireless door locks, smoke, fire, and intrusion detection and more. SoC designers building chips for these applications need a feature rich 32-bit computing platform that provides a roadmap to enhanced functionality over time. The AndesCore™ N8 with its 3-stage pipeline design boosts the execution efficiency of today's computation algorithms, reduces memory usage, lowers customers' silicon cost, while providing a long-term roadmap for customers needing an upgrade path from 8-bit cores.
Motion, magnetic, pressure, light and temperature sensors are at the heart of IoT devices for home automation. Embedded processors to control these sensors and communicate their readings to the web must be power efficient enough to run on batteries sometimes last more than 10 years, for example the intrusion sensors on door and windows. The N8 achieves 1.82 DMIPS/MHz, which are far more computing power and energy conservation than its peers.
Embedded processors also need to be cost effective for integration into Internet of Things priced at a small fraction of today's mobile devices. The N8's ability to process both 16-bit and 32-bit instructions enables smaller ROM size for the program data, thus provided a computing platform whose program memory is comparable to that of an 8-bit controller, but performance is that of an advanced 32-bit processors.


  • Internet of Things (IOT)
  • Sensor hub
  • Smart thermostat controller
  • Home security/automation controller
  • Smart Gas/Water/Electronic meter
  • Personal health device
  • Wearable device
  • PC/Notebook peripheral

Block Diagram

Development Tools

  • AndeSight™ Integrated Development Environment
  • AICE JTAG/SDP debugger hardware

Key Features and Performance

AndeStar™ V3m+ Architecture
Key Features Benefits
21st-century RISC instruction set Better performance for modern compiler
V3 subset for MCU most frequency used instructions Smaller die size and lower power consumption
16/32-bit mixable opcode format Smaller code size
All-C Embedded Programming Faster SW development and easier maintenance
Advanced CoDense™ technology Program code size reduction
Hardware divider More performance
Direct support of up to 32 interrupts with programmable priority levels Quick identification of interrupt sources and fast assignment of service routines
4G/16MB address space Less address bits option leading to small gate count
Memory mapped IO Easy to program and friendly to compiler
CPU Core
Key Features Benefits
1.82 DMIPS/MHz* 
3.54 CoreMark/MHz*
Superior performance-per-MHz
3-stage pipeline Superior performance-efficiency, while allowing for high speeds
Branch predication Better performance for branches
Choice of multipliers
  • Fast (1 cycle) for performance
  • Small (<0.5K gates) for size
Application specific configurations
  • More performance
  • Smaller size
Hardware stack protection Stack size determination and runtime overflow error detection
Processor state bus Simplification SoC design and debugging
Performance monitors Program code performance tuning
Interface to FlashFetch IP (separately licensable) which contains following options
  • Prefetching functionality
  • Caching functionality
  • SPI interface to external flash
Slow flash memory acceleration and power consumption reduction
Extensive clock gating and logic gating Lower power
N:1 core/bus clock ratios Simplified SoC integration
Low-latency vectored interrupt Faster context switch for real-time applications
Completion of most operations in 1 cycle Single-cycle capable for Local Memory and AHB bus accesses Better performance-efficiency
PowerBrake technology Peak power consumption reduction

* BSP v4.2.0, DMIPS/MHZ without no-inline option, best performances

Memory Subsystems
Key Features Benefits
Optional External Instruction and Data Local Memory
  • Size: 0KB to 4MB
  • ILM: program code, data and IO
  • DLM: program data and IO
Higher efficiency for program execution
  • Flexible size selection to fit diversified needs
  • Capable of replacing DLM and bus for lower cost
  • Capable of replacing bus for lower cost
BIU supports AHB-lite or APB User-selectable bus interface for optimal efficiency
Debug Support
Key Features Benefits
2-wire Serial Debug Port or 5-wire JTAG Debug Port Low-cost 2 wire support and industry-standard 5-wire support
Embedded Debug Module (EDM)
  • Up to 8 breakpoints and watchpoints
  • Secured debug access to system address space
  • Flexible configurations to trade off gate count and debugging capabilities
  • Code and data protection by allowing only authorized debugging
Process 90LP 40LP 28HPM
Frequency (MHz) 50 50 50
Dynamic power (uW/MHz) 12.2 5.2 3.1
Area (mm2) 0.047 0.017 0.008

* Base configuration, RVT library. ; Power consumption iat typical process corner, Vdd (90LP: 1.2V, 40LP:1.1V, 28HPM: 0.9V), 25°C

Process 40LP 28HPM
Max frequency (MHz) 529 846
Dynamic power (uW/MHz) 9.1 6.6
Area (mm2) 0.032 0.017

* Base configuration,  LVT library; Frequency at slow process corner, 40LP: 0.99V, 28HPM:0.81V, 125°C and without I/O constraint; Power consumption at typical process corner, Vdd (40LP:1.1V, 28HPM: 0.9V), 25°C