AndesCore™ E8 Overview

  • Best in its class per-MHz performance
  • Andes Custom Extension™ (ACE) for significant performance efficiency boost
  • Small footprint with low gate count and high code density
  • Speed-up and power reduction for Flash accesses by FlashFetch technology

The new Andes Technology E8 CPU processor core targets Internet of Things (IoT) applications with the unique Andes Custom Extension™ (ACE) on a power-efficient compact embedded controller. SoC designs for IoT devices demand low power consumption in combination with high performance to handle compute intensive functions such as processing sensor data and wireless protocol stacks. The E8's unique ACE environment enables designers to specify the architectural element that makes the core ideal for IoT applications. With Andes' Custom-OPtimized Instruction deveLOpment Tools (COPILOT), designers can create custom instructions that differentiate their design from competitive offerings, which are based on standard instruction set processors. By adding special instructions, not easily discoverable by hackers, ACE also provides stronger security to a design.
 
Another E8 feature, FlashFetch, boosts performance while saving power. FlashFetch consists of a small amount of buffer near the processor core that enables repetitive functions to be executed efficiently thus eliminating power consuming flash memory accesses. With a three-stage pipeline, the E8 can achieve 1.82 DMIPS per MHz, which is far higher performance than other 32-bit alternatives while the power consumption and gate-count are as low as 8-bit controllers.

Applications

  • Connectivity device
  • Sensor hub
  • Wearable device
  • Smart meter
  • Storage device
  • Touch screen controller
  • Battery management
  • Sensor-less motor driver

Block Diagram

Development Tools

  • COPILOT Custom optimized instruction development tool
  • AndeSight™ Integrated Development Environment
  • AICE JTAG/SDP debugger hardware

Key Features and Performance

AndeStar™ V3m Architecture
Key Features Benefits
21st-century RISC instruction set Better performance for modern compiler
V3 subset for MCU most frequency used instructions Smaller die size and lower power consumption
16/32-bit mixable opcode format Smaller code size
All-C Embedded Programming Faster SW development and easier maintenance
Hardware divider More performance
Direct support of up to 32 interrupts with programmable priority levels Quick identification of interrupt sources
Fast assignment of service routines
Andes Custom Extension™ (ACE) Performance boost with customized instructions
16MB address space Reduced core size with optimum memory support
Memory mapped IO Friendliness to programmers and compilers
CPU Core
Key Features Benefits
1.82 DMIPS/MHz*
3.54 CoreMark/MHz*
Superior performance-per-MHz
3-stage pipeline Superior performance-efficiency, optimum core size, while allowing for high speeds
Branch predication Better performance for branches
Return address stack Speed up procedure returns
Choice of multipliers
  • Fast (1 cycle) for performance
  • Small (<0.5K gates) for size
Application specific configurations
  • More performance
  • Smaller size
Hardware stack protection Stack size determination and runtime overflow error detection
Processor state bus Simplification of SoC design and debugging
Performance monitors Program code performance tuning
Interface to FlashFetch IP )separately licensable) which contains following options
  • Prefetching functionality
  • Caching functionality
  • SPI interface to external flash
Slow flash memory acceleration and power consumption reduction
Andes Custom Extension™ (ACE)
  • Simple and flexible interface
  • 1 cycle or multi-cycle instruction latency
  • Up to 3R/2W general-purpose register accesses
  • Logic sharing among custom instructions
  • Support user-defined error status
  • Support instruction interruption
  • Memory accesses through E8
  • ACE Registers (ACR) for more powerful instructions
  • Productive: improve SoC’s performance, speed, power, and cost with instruction customization
  • Flexible: program the custom instructions as needed
  • Secure: stop reverse engineering in program code by proprietary custom instructions
Extensive clock gating and logic gating Lower power
N:1 core/bus clock ratios Simplified SoC integration
Low-latency vectored interrupt Faster context switch for real-time applications
Completion of most operations in 1 cycle
Single-cycle capable for Local Memory and AHB bus accesses
Better performance-efficiency and low latency
PowerBrake technology Peak power consumption reduction

* BSP v4.2.0, DMIPS/MHZ without no-inline option, best performances

Memory Subsystems
Key Features Benefits
Optional External Instruction and Data Local Memory
  • Size: 0KB to 4MB
  • ILM: program code, data and IO
  • DLM: program data and IO
Higher efficiency for program execution
  • Flexible size selection to fit diversified needs
  • Capable of replacing DLM and bus for lower cost
  • Capable of replacing bus for lower cost
BIU supports AHB-lite or APB User-selectable bus interface for optimal efficiency
Debug Support
Key Features Benefits
2-wire Serial Debug Port or 5-wire JTAG Debug Port Low-cost 2 wire support and industry-standard 5-wire support
Embedded Debug Module (EDM)
  • Up to 8 breakpoints and watchpoints
  • Secured debug access to system address space
  • Flexible configurations to trade off gate count and debugging capabilities
  • Code and data protection by allowing only authorized debugging
Performance
Process 90LP 40LP 28HPM
Frequency (MHz) 50 50 50
Dynamic power (uW/MHz) 11.7 5.1 2.8
Area (mm2) 0.04 0.016 0.008

* Base configuration, RVT library ; Power consumption at typical process corner, Vdd (90LP: 1.2V, 40LP: 1.1V, 28HPM: 0.9V), 25°C

Process 40LP 28HPM
Max frequency (MHz) 538 838
Dynamic power (uW/MHz) 9.5 6.6
Area (mm2) 0.032 0.015

* Base configuration, LVT library; Frequency at slow process corner, 40LP: 0.99V, 28HPM:0.81V, 125°C and without I/O constraint; Power consumption at typical process corner, Vdd (40LP:1.1V, 28HPM: 0.9V), 25°C