| |
AMBA AHB bus for high speed devices
AMBA APB bus for low power devices
Dedicated DRAM interface for DMA and LCD Controller
AndeScore™ processor(s)
External Memory Interface
SDRAM/SRAM/ROM/Flash
Power Management
 |
Frequency division and clock gating control for variety
of devices |
Frequency scaling control for PLLs
Sleep Mode
On/off control for external main power
Power status input
AHB Bus Components
SDRAM Controller
Static Memory Controller
Ethernet MAC 10/100
DMA Controller
LCD Controller
USB2.0 Device Controller |
Timer
Watch Dog Timer
Real Time Clock
Interrupt Controller
GPIO
Pulse Width Modulator
I²C
Synchronous Serial Port
I²S / AC97
Compact Flash Controller
Multimedia Card / Secure Digital Host Controller
Bluetooth UART (BTUART)
Standard UART (STUART)
Reference Operating Frequency
 |
100 MHz for AHB and 50 MHz for APB in UMC 0.13HS
process |
Development Tools
AndeSight™ and AndESLive™
ADP-AG101 hardware development platform |