|
|
| Home / Products Showroom / AndeScore™ |
|
General descriptions
N1213-S is a synthesizable softcore of general purpose 32-bit embedded processor, with variety of configuration options including MMU, cache and local memory. It can be configured for performance sensitive applications that running embedded Linux or other advanced operating systems, as well as cost and power sensitive applications that require small footprint and manageable power consumption.
N1213-S is delivered with complete development package for ease of integration in SoC design by its user-friendly configuration tool, simulation environment, as well as reference design flow to fit customer's requirement in all aspects of performance, power consumption and core size. |
|
|
| |
|
|
| |
Key Features |
| |
|
| |
CPU Core
 16-/32-bit mixable instruction format
32 general-purpose 32-bit registers
8-stage pipeline
Dynamic branch prediction
32/64/128/256 BTB
Return address stack (RAS)
|
Vector interrupts for internal/external
interrupt controller with 6 hardware interrupt signals |
3 HW-level nested interruptions
User and super-user mode support
Memory-mapped I/O
Address space up to 4GB |
|
| |
|
| |
Memory Management Unit
TLB
 4/8-entry fully associative iTLB/dTLB
32/64/128-entry 4-way set-associative main TLB
TLB locking support
Optional hardware page table walker
Two groups of page size support
4KB & 1MB
8KB & 1MB |
|
| |
|
| |
Memory Subsystem
I & D cache
I & D local memory (LM)
| |
Size: 4KB to 1MB
Bank numbers: 1 or 2
Optional 1D/2D DMA engine
Internal or external to CPU core |
|
| |
|
| |
Bus Interface
|
Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports |
|
Synchronous High speed memory port
(HSMP): 0, 1 or 2 ports |
|
|
| |
|
| |
Debug
JTAG debug interface
Embedded debug module (EDM)
Optional embedded program tracer interface |
|
| |
|
| |
Miscellaneous
Programmable data endian control
Performance monitoring mechanism |
|
|
|
| |
Benefit |
| |
|
| |
Performance
Versatile memory access instructions
Burst support for uncached load multiple
|
Efficient atomic access synchronization
without locking system bus |
|
Low latency vectored interrupt improving
real-time performance |
|
Zero-wait-state local memory with 1D/2D DMA |
MMU
| |
Optional HW page table walker |
| |
TLB management instructions |
Flexibility
Memory-mapped IO space
PC-relative jumps for position independent code
JTAG-based debug support
Performance monitors for performance tuning
Bi-endian
Power Management
Clock-gated pipeline
Low-power mode support instructions |
|
| |
|
| |
Applications |
| |
|
| |
Digital TV
Digital Home
Set top Box
MFP
Switch/Router
Communication
Smart Phones |
| |
|
| |
Development Tools |
| |
|
| |
AndeSight™ : Integrated development environment
AndESLive™ : ESL integrated virtual environment |
|
|
|
|
|
|
Overview
Site map