Press Release

Andes Technology Corp. Targets Deeply Embedded Protocol Processing and Entry-level MCUs With the New N22, the Smallest RISC-V Core in its V5 Family


N22 Delivers up to 3.93 CoreMark/MHz, in as little as 15K Gates with Highly Flexible Interfaces and Debug Support

HSINCHU, TAIWAN--Andes Technology Corporation, a leading supplier of small, low-power, high performance 32-/64-bit embedded CPU cores, including a broad family of RISC-V processors, announces the new N22 32-bit RISC-V CPU core to target deeply embedded protocol processing such as high-speed communication and storage, and entry-level MCU applications such as small IoT and wearable devices. The highly configurable N22 is the smallest in the Andes RISC-V family offerings in just 15K gates with minimum useful configuration settings, and yet delivers over 750MHz at 28nm in the worst case. In addition, the N22 provides an impressive 3.93 CoreMark/MHz, highly flexible system and memory interfaces and vector interrupt controller. In addition, a low pin count two-wire debug module can save SoC chip cost, and a pre-integrated MCU platform with frequently used peripherals can help speedup construction of various SoCs.

“CPU cores to serve today’s high-speed communications and storage markets must be able to do more than run at a high data rate,” declares Andes Technology President Frankwell Jyh-Ming Lin. “The protocol SoCs serving these markets are highly complex to meet widely diverse applications.  As a result, SoCs need to offer not only high bandwidth processing to accommodate the data rate, but also software based flexibility when new standards and protocols are adopted by the industry standards groups in these markets.  Furthermore, silicon costs dictate ultra-small gate counts to serve anywhere within the SoC design, especially when dozens of instances are needed. The N22’s high performance and compact design makes it very suitable to process on-the-fly protocol packets at high data-rate. ”

“The N22 is a 2-stage pipeline core with small gate count which can fit in entry-level MCU applications such as small IoT and wearable devices. It supports 16 or 32 GPRs (general purpose registers), optional branch prediction, hardware multiplier and divider, vector Interrupt Controller, and Andes V5 extensions,” stated CTO and Senior Vice President, Dr. Charlie Hong-Men Su.  “In addition to Andes’ professional development environment, the N22’s RISC-V RV32IMAC or RV32EMAC ISA compatibility opens up the full suite of compiler, debugger, ICE/trace probe tools from RISC-V Foundation’s rich ecosystem. The N22 leverages Andes’ long track record of CPU development, including the high-volume N7/N8 families with efficient short pipelines and many useful features such as StackSafe™ for hardware stack protection, CoDense™ for code size compression, and PowerBrake for power management.  Moreover, the new N22 will be available with a rich set of system level configuration options such as Physical Memory Protection (PMP), Platform-Level Interrupt Controller (PLIC), cache and local memories, private bus interface, and fast IO interface with 0-cycle latency.” 

Price and Availability 
The N22 pricing will be consistent with current Andes licensing and royalty business model.  The core will be available in February, 2019 for initial customer delivery.