Andes

Majority of network protocol features many sparse data manipulations for protocol handshaking, while requires significant memory bandwidth to bring network packets in and out of each processing engine. This nature sometimes drives more processor loads on moving data in and out versus the loads on actually processing the data. Thus the bandwidth and latency for software to access memory containing network packets has become very critical to an embedded system. Unfortunately, since the life time of a network packet in an embedded system is usually very short, the worse locality nature of this kind of data usually degrades the efficiency of a processor cache when cache is needed to benefit the efficiency of entire system software.

AndeScore™ Solution for Networking
To improve networking processing efficiency for majority of embedded systems, AndeScore™ has designed with an unique memory subsystem architecture that greatly reduce memory access latency, increase data transfer efficiency, while still maintain best cacheability for the entire system software. The in-pipe local memory structure offers single cycle memory access to software in additional to existing L1 cache structure. In addition, the internal local memory DMA may work in advance to bring data into local memory for fast software processing (and out of it after processing) without consuming any additional main pipeline resource for the trivial data transfers. In summary, below please see a list of features AndeScore™ solution benefits networking applications:

	In-pipe internal local memory structure allows 1-cycle load/store access, which is useful for packet header processing by software without degrading cache efficiency.
	External local memory allows dynamic wait states to be inserted for the applications to share the local memory between processor main pipe and other hardware engines that could direct access the shared local memory.
	Virtual address accessible local memory architecture eliminates unnecessary memory copy between kernel modules and user programs for the applications that require packet processing in user programs.
	Double-buffer capable internal local memory DMA can be used to bring data into and out of local memory without impacting software operations in processor core.
	The context-switchable feature of the DMA engine allows user program working with DMA channels directly, which eliminate system call overhead between user program and OS.
	Unaligned DMA transfer and load/store operations eliminate unnecessary excessive memory access for networking packet header alignment.
	Dynamic endian conversion and unaligned data transfer features, which are generally required during network protocol handling, also boost efficiency of networking packet process significantly.
	Virtual-index-physical-tag cache structure generally enhances context switching efficiency for multi-process systems that commonly implemented for networking products.
	Multiple-word load/store operations help networking software a lot on general header processing and data framing, as well as queuing and buffering operations.
	Post-increment address mode load/store instructions are very useful to networking software that would require significant data walking and/or table lookup.