Andes Presents Ground-Breaking 27-Series Processor at RISC-V Summit 2019

Configurable Vector Processor Enables Scalable Performance Beyond Any IP Core to Date Supported by High-Performance Memory Subsystems

Hsinchu, Taiwan and San Jose, California, December 4th, 2019 – Andes announces AndesCore™ 27-series CPU cores today and will present it at the RISC-V Summit.  The 27-series is the first licensable RISC-V core to deliver to a production licensee the RISC-V Vector instruction extension (RVV), and to sustain the memory bandwidth and efficiency Andes has also re-architected its memory subsystem.  Initial delivery of the CPU core has completed to Andes earliest licensee, with production release slated for Q1, 2020.  Dr. Charlie Su, Andes Technology CTO and EVP will unveil details of this ground-breaking product at the Summit. 

The advent of AI, AR/VR, computer vision, cryptography, and multimedia processing all require complex computation of large volume of matrix data.  Unlike other vendor’s advanced SIMD, which has a narrow range of performance dictated by their architecture control, the RVV specification envisions a powerful instruction set with scalable data sizes, flexible microarchitecture implementations, and leaves memory subsystem decisions open for system level optimization.  With the 27-series CPU cores, Andes delivers this unprecedented performance and flexibility to the RISC-V community and for the first time, enables RISC-V cores to fill the void in applications even other vendors have not been able to reach. 

“The 27-series marks yet another important milestone in both Andes and RISC-V journey, and I couldn’t be more proud of our R&D team for this achievement,” said Andes President, Frankwell Lin. “The RVV extension boldly takes RISC-V beyond any licensable processor core technology into the hottest markets today, and our licensee’s confidence in the R&D team enables Andes to be the first to deliver on this ambitious vision.  The team has worked together from specification to delivery in less than nine months.  It’s one of the most thrilling journey in Andes history.”

Initially available in the 27-series will be the 32-bit A27, and 64-bit AX27 and NX27V. They benefit from Andes proven 25-series cores, supporting the latest RISC-V specifications, subsystem level components, as well as ecosystem enablement from Andes’ 14-years of R&D development.  The A27 and AX27, tailored for applications running Linux, offer 50% higher memory bandwidth than its 25-series predecessors. The NX27V contains a Vector Processing Unit (VPU) which supports the RVV scalable vector instruction set, designed from the ground up to be a Cray-like full vectorization computation unit than the incremental growth from SIMD instructions which some advanced SIMD has evolved from.  As such, there is a full Vector Register File (VRF) of user-configurable number of elements per register.  Each vector can be arbitrary length, from as small as 64-bit to as large as 512-bit (VLEN) and all the way to 4096-bit by combining up to eight vector registers (LMUL).  It also allows each computation of integer, fixed point, floating point, and other AI-optimized representations to be any bit-width from 4 bits to 32 bits, and handles non-divisible last matrix elements in the same loop.  The 27-series VPU implements all of these capabilities, and has multiple functional units which are chainable, each can operate in independent pipelines to sustain the computational throughputs needed in critical kernel functions.  Fully configured, the VPU can achieve over 30x speedup measured by the key functions in MobileNets, a popular convolution neural networks (CNN).  Compared to the popular 128-bit scalar SIMD solution, the NX27V VPU offers 4 times more raw processing power per cycle with additional advantage due to the higher efficiency of vector instruction issuing.

“It’s exciting to see fourteen years of R&D investment all come together in one ambitious project,” said Dr. Charlie Su. “From the vector microarchitecture to the memory subsystem, and all the ecosystems required to enable our licensees, at whatever scale and scope the licensee deems appropriate, Andes has taken RISC-V users to the frontiers of these embedded applications.”

Indeed, the 27-series has vastly expanded its memory subsystem to keep up with the bandwidth required to sustain the computational rate of the VPU, all of which will benefit all customers in general, whether they use the VPU or not.  The 27-series now supports multiple outstanding memory accesses inflight so the scalar and vector processors both don’t have to wait for the data during cache misses.  In addition, cache pre-fetches allow the memory to prepare data in advance of processor’s needs, thus hiding potential cache misses.  Finally, Andes Custom Extension (ACE) interface has been expanded to provide instruction customization to speed up control path as well as to widen data path into the core.

 

Pricing and Availability:

The 27-series processor beta release has been delivered to Andes’ first licensee in early December, 2019, with production database release in Q1, 2020.  Please contact Andes Sales at sales@andestech.com for configuration and pricing of the 27-series processors.

About Andes Technology

Fourteen years after starting from scratch, Andes Technology Corporation is now a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment that serves the rapidly growing global market for embedded system applications. A founding Platinum member of RISC-V Foundation, Andes is the first mainstream CPU vendor that has adopted the RISC-V as the base of its fifth-generation architecture, the AndeStar™ V5. To meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores with full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC in a shorter time to market. Since 2018, the yearly volume of SoCs Embedded with Andes CPUs has surpassed the 1-billion mark. Andes Technology’s comprehensive RISC-V CPU families range from the entry-level 32-bit N22, mid-range 32-bit N25F/D25F/A25 and 64-bit NX25F/AX25F, to the high-end multicore A(X)25MP.

 

Continue ReadingAndes Presents Ground-Breaking 27-Series Processor at RISC-V Summit 2019

RISC-V Foundation Founding Member Andes Technology Turns Platinum

Leading RISC-V CPU IP provider deepens commitment to support the development of embedded computing and customized CPU

Hsinchu, Taiwan – December 03, 2019  –  Andes Technology Corporation (TWSE: 6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 1-billion diversified SoCs yearly, today announced that it has upgraded its membership in the RISC-V Foundation to Platinum.

Andes Technology joined the RISC-V Foundation in 2016 as a founding member and brought its extensive experience in developing embedded CPU and supporting diversified applications to take RISC-V ISA to the next level. With more than 300 commercial licenses and cumulative shipments exceeding 4 billion SoCs, Andes is the first public CPU IP vendor with the market and technology expertise driving the open-source RISC-V instruction set architecture. Andes’ commitment to the RISC-V community is rooted on its strong belief on open source. It is a major contributor and maintainer of RISC-V open source software such as GNU, LLVM, uBoot, and Linux. Moreover, as the chair of the P-extension (Packed SIMD/DSP) Task Group and co-chair of Fast Interrupt Task Group, Andes continues its key role contributing architecture extensions to the RISC-V Foundation. In addition, Andes also regularly attends the global Technical Committee meetings to closely watch and contribute to other Task Groups.

Andes also participates in the RISC-V Foundation Marketing Committee and APAC Promotion Task Group to help drive RISC-V’s global expansion. The company has joined most every RISC-V workshop in Asia, EU, and the US, and one-day RISC-V roadshows in 15 cities around the world. It participates in important industry events, such as Embedded World, DAC, RISC-V Meetups and many more. In 2019, Andes has given more than 100 public presentations relating to RISC-V promotion. To further promote RISC-V, Andes produces the successful RISC-V CON series across Asia and Silicon Valley aiming to share market trends and leading technology development with RISC-V enthusiasts around the world.

“Andes’ unwavering commitment to RISC-V has continued to inspire and engage the broader ecosystem. The RISC-V Foundation is honored to work with Andes in accelerating momentum and adoption of RISC-V around the world,” said Calista Redmond, CEO of the RISC-V Foundation.

“’The Global AI in IoT market is expected to reach $21.1 billion by 2026 growing at a CAGR of 27.1 percent during the forecast period,’” according to Esticast Research. Choosing a professional CPU IP provider is the key to the development of purpose-built SoCs and faster time to market to address this enormous opportunity. The open, compact, modular and extensible RISC-V ISA together with its extensive ecosystem is the perfect choice for these embedded SoCs,” said President of Andes Technology, Frankwell Lin. ”We are thrilled to upgrade our membership to Platinum and work even closer with the RISC-V community to solve application and persistent computing challenges for the embedded ecosystem.”

“We joined the RISC-V Foundation because the RISC-V ISA aligned almost perfectly with our original self-developed ISA. Our customers can continue to use their AndeSight™ IDE (Integrated Development Environment) simply by upgrading, and we can bring our years of experience in processor IPs and embedded systems to our new RISC-V users and customers.” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “AndesCore™ runs from one to more than 1,000 cores in a single SoC in which Andes provides a wide variety of solutions to empower our customers. By upgrading to a Platinum Member Representative, we will devote more resources to the RISC-V ecosystem and continuously bring more processor solutions to market, enriching the RISC-V product line. This helps drive our vision of Taking RISC-V Mainstream.”

About Andes Technology

After 14-year effort starting from scratch, Andes Technology Corporation is now a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve the rapidly growing global embedded system applications. Andes is also a founding Platinum member of RISC-V Foundation and the first mainstream CPU vendor adopted the RISC-V as the base of its fifth generation architecture, the AndeStar™ V5. In order to meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores with full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC in a shorter time frame. Since 2018, the yearly volume of Andes-Embedded™ SoCs has surpassed the 1-billion mark. Andes Technology’s comprehensive RISC-V CPU families cover from entry-level 32-bit N22, mid-range 32-bit N25F/D25F/A25 and 64-bit NX25F/AX25F, to the high-end multicore A(X)25MP.

For more information, please visit https://www.andestech.com

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Secure-IC and Andes Technology jointly provide cybersecurity enhanced RISC-V cores

Hsinchu, Taiwan– November 13, 2019 – Today, Secure-IC, the embedded security solutions provider from France specialized in embedded cybersecurity to protect against attacks, enters a strategic partnership with Andes Technology Corporation (TWSE: 6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 1-billion diversified SoCs yearly. This strategic partnership consists in delivering a secure high performance processor. Secure-IC’s Cyber Escort Unit™ associated with Andes RISC-V processors ensures a protection against both Physical and Cyber Attacks such as buffer overflow, fault injection attack, instruction skip or replacement and is compliant with high security levels (EAL) regarding the Common Criteria Certification and the PP0084 Protection Profile. In addition, the solution is fully aligned with the DARPA System Security Integrated Through Hardware and Firmware (SSITH) program.

AndesCore™ RISC-V processors, based on AndeStar™ V5 architecture, currently include the ultra-compact 32-bit N22 for entry-level microcontrollers and deeply-embedded protocol processing, the 32/64-bit N25F/NX25F for high-speed control tasks or floating-point intensive applications, the 32-bit D25F for signal processing applications, the A25/AX25 for Linux-based applications and the A25MP/AX25MP for cache coherence multi-core applications. To make them best fit application requirements, the 25-series processors offer optional key features such as dynamic branch prediction, instruction and data caches, local memories, floating point unit, and DSP extension. Leveraging its long track record of CPU technologies, Andes delivers its RISC-V processors with leading performance efficiency, and many advanced features such as StackSafe™ for hardware stack protection, CoDense™ for code size compression, and PowerBrake for power management. Moreover, Andes RISC-V cores are available with a rich set of system level configuration options such as Physical Memory Protection (PMP) and Platform-Level Interrupt Controller (PLIC).

The Secure-IC’s Cyber Escort Unit is designed to fill the security gap between software cybersecurity and hardware by escorting step by step the program execution to achieve high execution performance in a secure way, allowing real-time detection of zero-day attacks. Unique on the market, this product builds the foundation for hardware-enabled cybersecurity. It is the only tool on the market that comprises technologies for detecting and deceiving cyberattacks. This technology acts on-the-fly. Precisely, Cyber Escort Unit (Cyber EU in short) is a two-fold technology aiming to protect against four threats:

  1. Return oriented programming (ROP), Jump Oriented Programming (JOP): The attacker reuses chunks of code to assemble a malicious program as a patchwork.
  2. Stack Smashing, by exploiting a buffer overrun or integer under-or-overflow etc.: the attacker crafts some fake stack frames in order to change the program context.
  3. Executable Code Modification, overwrite: the attacker manages to change the genuine program into a malicious program.
  4. Control Flow hijacking: the attacker manipulates the program so that it calls an illicit function, or it takes an illicit branch.

Secure-IC’s solution is deterministic in timing and suitable for real-time application, such as mission-critical applications (e.g., safety requirements in automotive industry) & also suitable for cyber-physical systems, i.e., detecting issues irrespective they arise from physical alteration or cyber-attack.

“Cybersecurity becomes a real challenge because there are many connected devices, and attackers are becoming more and more destructive,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “We are very pleased to work with Secure-IC to provide the excellent cybersecurity solution to help our customers design robust IoT SoCs. With the integrated platform and FPGA demo ready solution of industry-leading Cyber Escort Unit from Secure-IC and the RISC-V processors from Andes, SoC designers can easily prevent hostile attacks from the outside world with outstanding performance and network security.”

Secure-IC CEO, Hassan Triqui said, “It is a pleasure to integrate our Cyber Escort Unit solution with Andes RISC-V processor. The integration of Cyber Escort Unit with Andes solution provides to customer a secure and high performance processor that protects the systems against security and safety threats. ”

Secure-IC flagship IP is the “Securyzr”, a root-of-trust solution for ensuring device security and offering security services (such as authentication, life cycle management, remote configuration and cloud on boarding). This security subsystem can embed a dedicated processing unit based on a standard or cybersecurity-enhanced AndesCore™ V5 processor. The Securyzr using Cyber Escort Unit-security enhanced AndesCore offers a resilience against various attacks such as Side Channel Attack, Fault Injection Attack and Cyber Attack.

About Andes

After 14-year effort starting from scratch, Andes Technology Corporation is now a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve the rapidly growing global embedded system applications. Andes is also a founding member of RISC-V Foundation and the first mainstream CPU vendor adopted the RISC-V as the base of its fifth generation architecture, the AndeStar™ V5. In order to meet the demanding requirements of today’s electronic devices, Andes delivers highly configurable and performance-efficient CPU cores with full-featured integrated development environment and comprehensive software/hardware solutions to help customers innovate their SoC in a shorter time frame. Since 2018, the yearly volume of Andes-Embedded™ SoCs has surpassed the 1-billion mark. Andes Technology’s comprehensive RISC-V CPU families cover from entry-level 32-bit N22, mid-range 32-bit N25F/D25F/A25 and 64-bit NX25F/AX25F, to high-end multicore A(X)25MP.

For more information, please visit https://www.andestech.com

About Secure-IC

Secure-IC has established a thought leadership position in the security world.

Secure-IC sets itself apart by accompanying customers along the IC design process by providing best in class protection embedded Secure Elements and security IP cores, security evaluation solutions & consulting services to reach the best available certification required for different markets.

Combining a full set of analysis platforms with best of breed set of security technologies & backed by almost 40 families of international & global patents, Secure-IC is considered a leader in cyberspace security embedded systems.  Secure-IC protects companies against attacks and guarantees at each stage of the design process that an optimal security level is reached.  The best of breed technologies that are provided stem from the company’s commitment to the research community, as a spin-off from Telecom Paris Tech University, in order to foresee future major threats, tackle problems with innovative solutions & empower the intricate work of the industry standardization bodies.  The company provides Silicon proven technology, pioneering in AI for embedded security, post quantum & hybrid, and state-of-the-art synthesis of attacks/ countermeasures.   The embedded security system lines can be better recognized as Threat Protection (A combination of smart units & expertise results), Threat Analysis (Ready to use, pre & post silicon & SW analysis platforms) and Think Ahead (the next steps towards all security challenges).

For more information about Secure-IC solution, click http://www.secure-ic.com  

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Andes Technology and Tiempo Secure Announce Strategic Partnership to Enhance RISC-V Platform Security up to CC EAL5+ Certification

HSINCHU (Taiwan) and GRENOBLE (France) , October 1st, 2019 Andes Technology Corporation, a leading supplier of outstanding efficiency, low-power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC-V cores, has entered into a strategic partnership with Tiempo Secure, a unique supplier of ISO/IEC 15408 standard CC (Common Criteria) EAL5+ (Evaluation Assurance Level) grade secure element IP, to bring the RISC-V based security solution up to CC EAL5+ certification.

The rise of IoT is driving serious concern about security, including at the edge device level. According to recent Ericsson research, by 2024, there will be more than 22 billion connected IoT devices. While security based from separation mechanism is commonly deployed, it is admitted that there is some limitation in term of security certification. Furthermore, security integration into the IoT ecosystem could become complex.

The alternative is to enable security from a tamper resistant and certified hardware as a security enclave (Secure Element IP) into the MCU or SoC design.

Tiempo Secure has developed a Secure Element IP (TESIC) as a hard macro integrating CC EAL5+ grade state-of the-art security countermeasures and security sensors against side channel and intrusion attacks. The integration of this Secure Element IP into a RISC-V SoC will bring the security of this SoC up to CC EAL5+ security, without compromising on power consumption.

“Andes Technology offers RISC-V based ultra-compact processor with the outstanding performance and low power consumption available on the market,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “Integrating Tiempo Secure’s CC EAL5+ security enclave into AndesCore N22 solution will now allow our customers to address the most security critical applications on the IoT market.”

“By working with Andes Technology we’re able to dramatically enhance the security that developers need to protect their IoT ecosystems based on RISC-V,” said Serge Maginot, CEO of Tiempo Secure. “The plug-and-play integration of TESIC, our CC EAL5+ grade Secure Element IP, into the RISC-V cores of Andes Technology will enable RISC-V developers to easily integrate certified security features, such as secure boot, secure firmware update or iUICC stack, into their system.”

Once the Secure Element IP from Tiempo Secure is embedded into the RISC-V based AndesCore N22 designed by Andes Technology, the whole system can pass the highest level of security certification, including CC EAL4+/EAL5+ PP0084 and FIPS 140-2. It also solves the problem of security integration into the IoT ecosystem.

About Andes Technology

Andes Technology Corporation is a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve the rapidly growing global embedded system applications. The company delivers superior low power CPU cores, including the comprehensive RISC-V V5 family of processor cores, with integrated development environment and associated software/hardware solutions for efficient SoC design. Up to the end of 2018, the cumulative volume of Andes-Embedded™ SoCs has reached 3.5 billion with 2018 alone contributing over 1 billion. Andes Technology’s comprehensive CPU line includes entry-level, mid-range, high-end, extensible and security families. For more information, please visit www.andestech.com

About Tiempo Secure

Tiempo Secure is an independent company founded by semiconductor industry experts having unique experience in the development of secure microcontrollers and embedded secure software. The company has already designed and certified Common Criteria EAL5+ and EMVCo secure microcontroller chips, available in contact and dual interface mode, for Government ID and High-end Banking applications. Tiempo Secure is now offering CC EAL5+ proven/certification-ready Secure Elements for the IoT market, either as companion chips or as hard IP macros that are easy to integrate into application/SoC chips, allowing the customer chips to pass CC EAL5+ and other security standard certification.

The company is headquartered in Montbonnot, near Grenoble, France. More information can be found at www.tiempo-secure.com

Continue ReadingAndes Technology and Tiempo Secure Announce Strategic Partnership to Enhance RISC-V Platform Security up to CC EAL5+ Certification

Andes and Dover Microsystems Partner to Deliver Professional Network Security Solution for RISC-V

HSINCHU, TAIWAN , Sept. 25, 2019 – Andes Technology Corporation (TWSE: 6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 1-billion diversified SoCs yearly, and Dover Microsystems, the first company to immunize processors against entire classes of network-based attacks, announced a strategic partnership to deliver professional network security solution for RISC-V. Dover’s CoreGuard® technology is the only solution for embedded systems that prevents the exploitation of software vulnerabilities. Dover’s CoreGuard silicon IP integrates with Andes RISC-V processors to protect against 94% of known software vulnerabilities, including 100% buffer overflows, code injection, and data exfiltration as well as safety violations.

Andes RISC-V processors are based on AndeStar™ V5 architecture, which maintains the full compatibility to RISC-V technology and thus inherits its compact, modular and extensible advantages. In addition, AndeStar V5 architecture brings Andes-extended features already proven in high-volume V3 AndesCore™ processors to be effective and beneficial to embedded applications with enhanced performance, code size and development support. Andes RISC-V cores include ultra-compact 32-bit N22 for applications such as entry-level microcontrollers and deeply-embedded protocol processing, 32-bit D25F for signal processing applications, 32/64-bit N25F/NX25F for high-speed control tasks or floating-point intensive applications, A25/AX25 for Linux-based applications and A25MP/AX25MP for cache coherence multi-core applications.

Dover Microsystems’ CoreGuard silicon IP acts as a bodyguard to the host processor, monitoring every instruction executed to ensure that it complies with a defined set of security, safety, and privacy rules – called micropolicies – that precisely define allowed versus disallowed behavior. CoreGuard maintains micropolicy-relevant metadata about every word in memory, and then uses this metadata to crosscheck each instruction processed against the installed set of micropolicies. If an instruction violates any micropolicy, CoreGuard Policy Enforcer hardware stops it from executing before any damage is done. CoreGuard Policy Enforcer RTL is licensed and delivered as a set of hardware SystemVerilog design files. Dover includes the base set of CoreGuard micropolicies that protect all embedded systems.

“Andes is determined to provide the best RISC-V solutions to help our customers design SoC exceeding their expectations. We understand that network security is a major concern of many IoT applications,” said Dr. Charlie Su, CTO and Executive VP of Andes Technology. “With the pre-integrated, verified solution of industry-leading CoreGuard technology from Dover Microsystems and the leading performance-efficient RISC-V processors with rich features for embedded systems from Andes Technology, SoC designers gain quick access to a mature RISC-V solution with outstanding performance and network security.”

“Our CoreGuard silicon IP integrates with existing RISC processors to protect embedded systems against security, safety, and privacy threats,” said Jothy Rosenberg, Founder and CEO of Dover Microsystems. “The integration of CoreGuard with the high-quality AndesCore RISC-V processor is clean and straightforward, providing customers with the most powerful and easy to adopt security solution that immunizes SoCs against network-based cyberattacks.”

For more information about Andes RISC-V processors, click http://www.andestech.com/markets.php.
For more information about Dover Microsystems CoreGuard®, click https://www.dovermicrosystems.com/solutions/coreguard

Continue ReadingAndes and Dover Microsystems Partner to Deliver Professional Network Security Solution for RISC-V

Andes Technology Announces Coming Up the North America Annual RISC-V CON 2019 Santa Clara

Santa Clara, US – September 24, 2019 – The RISC-V CON 2019 held in Santa Clara on October 15 will feature the first independent analysis of the commercial potential for the open source architecture RISC-V market opportunity. Jim Feldhan, President of Semico Research will present the findings of his firm’s evaluation based on research commissioned by the RISC-V Foundation. Amazon will provide a RISC-V user’s perspective in a technical presentation detailing an AI compiler based on RISC-V. Imperas will release their next generation software tools for developing RISC-V based SoCs. Faraday will offer a design service’s viewpoint on building a RISC-V based ASIC solution for edge AI and IoT SoC.

Andes Technology CTO and Executive VP Charlie Su, will present “Powering RISC-V SoCs with 1 to 1,000s AndesCores.” His presentation will illustrate the range and versatility of the RISC V instruction set architecture (ISA) that is propelling the ISA’s widespread adoption by everyone from start-ups to Fortune 500 companies in applications spanning Internet of Things to multiprocessor AI devices. To conclude up the seminar, a panel moderated by Jim Feldhan will discuss how Andes, Amazon, Imperas and Faraday are driving RISC-V adoption.

During RISC-V CON, presentations, partner exhibitions and live demo will enable attendees to learn more about the advanced RISC-V ISA technology. Through face-to-face interactions with RISC-V ecosystems and partners, attendees will get more latest, leading-edge information on this rapidly emerging new CPU architecture. For more information about RISC-V CON, please visit http://www.andestech.com/Andes_RISC-V_CON_2019_US/

About RISC-V CON
In order to foster stronger collaboration on RISC-V across the computing industry, RISC-V CON focuses on this disruptive technology, demonstrating its benefits and identifying commercial strategies. Through RISC-V CON, the RISC-V community and ecosystem can share the most up-to-date development and RISC-V based products and solutions.

With more than 14 years focusing on the CPU IPs, Andes Technology, the most experienced vendor of RISC-V processors and solutions, has launched many new RISC-V based products. By bringing together industry experts, the goal is to make it easier for other industry players to quickly bring innovative designs based on the open RISC-V ISA to market.

Continue ReadingAndes Technology Announces Coming Up the North America Annual RISC-V CON 2019 Santa Clara

Andes Technology Features 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors With Andes Custom Extension at TSMC 2019 Open Innovation Platform® Ecosystem Forum

A25MP and AX25MP are Cache Coherent RISC-V Multicore Processors
With Comprehensive DSP Instruction Extension and Custom Extensions for AI and ADAS Designs

HSINCHU, TAIWAN – September 24, 2019 – Andes Technology Corporation, a leading supplier of small, low-power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC-V cores, announced that it will be participating in the TSMC 2019 Open Innovation Platform® Ecosystem Forum, on September 26, 2019 at the Santa Clara Convention Center. Andes Technology will feature its latest generation 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors with Andes Custom Extensions, that allows designers to create special instructions to accelerate compute intensive functions, a capability highly desired in AI and ADAS designs. The cache coherent A25MP and AX25MP RISC-V multicore processors are the company’s first with comprehensive DSP instruction extension based on the RISC-V P-extension draft Andes donated to the RISC-V Foundation.

“The A25MP and AX25MP have already achieved major design wins in high-performance artificial intelligence applications and the product family has seen strong interest from Fortune 500 companies,” said Andes Technology Corp. President, Frankwell Lin. “Multiple processor cores extended with Andes Custom Extensions working in parallel enable computation intensive applications, such as artificial intelligence and Advanced Driver-Assistance Systems (ADAS) to significantly boost their performance. Furthermore, the DSP/SIMD ISA, executing the CIFAR-10 dataset (Canadian Institute For Advanced Research) image classification benchmark for machine learning achieved an order of magnitude performance boost. It also achieved 7 times acceleration in the PNET for MtCNN (Multi-task Cascaded Convolutional Networks) face detection and alignment algorithm.”

“The A25MP and AX25MP support up to four CPU cores,” said Dr. Charlie Su, CTO and EVP of Andes Technology Corp. “The processors’ hardware-managed cache coherence simplifies software design considerably for systems with multiple CPUs. They provide efficient cache coherence among private level-1 caches, include an optional shared level-2 cache and support I/O coherence for bus masters without caches. Besides that, using Andes Custom Extension™ (ACE) designers can increase performance by adding their own CPU instructions specifically for the target applications on the already optimized AndesCore™ processors and eliminate the software bottlenecks. Operating at over 1GHz in a 28nm process with Linux symmetric multiprocessing (SMP) support, the A25MP and AX25MP raise the RISC-V processors to the next performance level and widens its market potential.”

For more information about the A25MP/AX25MP multicores, please visit Andes Technology Corp. in booth 308 at TSMC 2019 Open Innovation Platform® Ecosystem Forum exhibition on September 26, 2019 at the Santa Clara Convention Center. In addition, please see Andes Technology Corp.’s presentation “Implementing Customized RISC-V CPUs in Machine Learning Applications,” in TSMC 2019 Open Innovation Platform® Ecosystem Forum printed proceedings. You can also learn about the A25MP and AX25MP cores as well as all Andes CPU core on our website http://www.andestech.com/en/products-solutions/andescore-processors/

Continue ReadingAndes Technology Features 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors With Andes Custom Extension at TSMC 2019 Open Innovation Platform® Ecosystem Forum

SEGGER Makes Its Entire Ecosystem of Tools Available for AndesCores

MONHEIM, GERMANY – September 18, 2019 – SEGGER, leading supplier of software libraries, development tools, debug probes and flash programmers, together with Andes, a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores, today announce their collaboration to support the complete development process of embedded systems based on Andes RISC-V CPUs with easy to use, efficient and reliable, tools and libraries.

The entire palette of SEGGER software libraries, from the RTOS embOS to file system, compression, graphics library, security, communication and IoT, as well as SEGGER’s integrated development environment Embedded Studio, already support all of Andes RISC-V processors. SEGGER’s J-Link debug probes and Flasher flash programmers currently support Andes RISC-V 32-bit CPU cores, including N25F, D25F and A25, with support for 64-bit CPU cores in the works.

Andes Technology Corporation is a leading embedded processor intellectual property supplier. Since 2005, the company has developed high-performance, low-power processors and their associated SoC platforms to serve the rapidly growing global embedded system applications. Up to the end of 2018, the cumulative volume of Andes-Embedded™ SoCs has reached 3.5 billion with 2018 alone contributing over 1 billion.

“We are excited to cooperate with Andes,” says Ivo Geilenbrügge, Managing director of SEGGER. “Our software tools and libraries, especially J-Link and Embedded Studio, significantly enhance the Andes RISC-V ecosystem. We offer a comprehensive one-stop solution for firmware and application developers.”

“We are excited to partner with SEGGER and have their entire product palette available to our RISC-V cores,” comments Dr. Charlie Su, CTO and Executive VP, Andes Technology Corporation. “SEGGER provides a complete ecosystem for all embedded needs. With J-Link and Embedded Studio, Andes now has the leading development solution. Fast and powerful: It simply works. Together, we offer powerful solutions for Andes V5 RISC-V extended ISA to serve diversified SoCs from our customers.”

For more information about SEGGER development solutions, click https://www.segger.com/

For more information about Andes RISC-V processors, click http://www.andestech.com/en/risc-v-andes/

Continue ReadingSEGGER Makes Its Entire Ecosystem of Tools Available for AndesCores

Andes Records Rapid Growth of RISC-V Processors Licensing Agreements in the First Half of 2019

Andes Signed over 60 RISC-V IP License Contracts in the First Half of 2019 Serving Multiple Applications throughout Many Countries Worldwide

HSINCHU, TAIWAN – August 6, 2019 – Andes Technology Corporation, a leading supplier of outstanding efficiency, low-power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC-V cores, announced it achieved a record of 60 licensing agreements for its new family of RISC-V processors during the first half of 2019. After working in the CPU IP field for many years, Andes Technology joined the RISC-V Foundation as a founding member in 2016, while keeping innovating new high-quality RISC-V products. Now the design wins are going into a wide range of applications, including artificial intelligence designs, where RISC-V plays an important role. Other applications adopting RISC-V include ADAS, blockchain, communications, IoT security platform, FPGA, IoT, data center server applications, and solid-state storage devices.

In 2019, Andes launched more series of new RISC-V cores. It includes the innovative 32-bit A25MP and 64-bit AX25MP, multi-core processors supporting up to four CPU cores that provide efficient cache coherence among private level-1 caches. The A25MP and AX25MP also support Linux with complete DSP instruction set. In addition, Andes’ new 32-bit D25F is a low-power, high-performance core with DSP instruction set that serves DSP applications without Linux. Andes’ 32-bit A25 and 64-bit AX25 which support Linux and floating-point operations have also been upgraded to support the DSP instruction set. Andes’ popular 32-bit N22 provides flexible configurability and high efficiency. With its short 2-stage pipeline it achieves impressive performance of 3.95 CoreMark/MHz that makes it suitable in entry-level MCU applications such as small IoT and wearable devices. With years of experience in developing and supplying CPU IP, Andes Technology has accurately grasped the real needs of customers for RISC-V core processors and has achieved the greatest competitive advantage.

Because of features such as open-source ISA, compact, modular and extensible, RISC-V’s market potential has aroused widespread attention and future development. In China, with government support, many RISC-V enthusiasts are actively involved in developing a wide range of RISC-V applications. This RISC-V boom has accelerated industry acceptance and has generated a flourishing hardware and software RISC-V ecosystem. Andes’ customers have achieved significant technology advancements, such as integrating large numbers of CPU cores on a single chip for efficient multiplexed calculations in applications such as AI.

In the first half of 2019, Andes launched the RISC-V FreeStart program offering its commercial-grade CPU N22 RISC-V core with no upfront license fee. The fast and easy FreeStart authorization process has achieved record responses from the industry and academic institutions, and it will help proliferate the number and variety of RISC-V applications.

“The growth of the RISC-V market is only in its infancy,” stated Andes Technology President Frankwell Jyh-Ming Lin. “Our customers’ applications are very diverse and include AI, IoT, ADAS, Netcom and consumer electronics. Customers choose Andes RISC-V solutions because of the technical support of its RISC-V products line, friendly interface and excellent products and solutions. Andes will continue to invest in developing RISC-V related products and environment, and work together with customers and partners to win new business opportunities.”

“Andes supports the technical and marketing committees of the RISC-V Foundation,” declared Andes CTO and Executive Vice President, Charlie Hong-Men Su. “In addition to contributing to the core technology and cooperating with the world’s major companies to develop the RISC-V architecture, Andes leads the latest trends in RISC-V technology. Andes’ advantage is that designers can customize the RISC-V IP product to optimize the CPU IP and expand the function for further enhancement of the overall performance. Custom instruction extensions are easily added using Andes Custom Extension™ (ACE). In addition, Andes’s RISC-V customers can also avail themselves of Andes technology including StackSafe™ for hardware stack protection, CoDense™ for code size compression, PowerBrake for power management and the professional software development environment AndeSight™ IDE for acceleration SoC development.”

About Andes RISC-V Contributions
In addition to expanding its product line and application areas, Andes also actively participates in the RISC-V communities and promotes its diverse marketing activities. Andes has taken part in more than 30 industry events that promoting RISC-V technology around the world in the first half of 2019. RISC-V CON in Shanghai, Shenzhen, Beijing and Hsinchu is an annual series of RISC-V workshops. The attendees engaged with one another and conduct in-depth discussions with speakers. Andes also participated in other activities including the RISC-V Foundation RISC-V Workshop organized in Hsinchu and Zurich and the RISC-V one-day seminar in nine cities in the US and China. Andes joined TSMC OIP (Open Innovation Platform) Forum in Europe to speak about RISC-V applications implemented in TSMC processes. These activities promote potential customers’ understanding of the RISC-V architecture and accelerate the expansion of the RISC-V ecosystem. RISC-V CON’s series of activities will be held in Silicon Valley on October 15 and in Beijing on November 14 during the second half of 2019. The speaker partners include major RISC-V technology industry contributors, such as the expert from Amazon. RISC-V CON continues to bring the latest RISC-V trends to its expanding audience.

Continue ReadingAndes Records Rapid Growth of RISC-V Processors Licensing Agreements in the First Half of 2019

Andes Technology and Silex Insight Announce Strategic Partnership for RISC-V Based Root-of-Trust IP Solutions

July 1, 2019

Andes Technology, Hsinchu, Taiwan

Silex Insight, Mont-Saint-Guibert, Belgium

Andes Technology, a leading Asia-based supplier of high-performance low-power compact 32/64-bit RISC-V CPU cores, and Silex Insight, a leading provider for flexible security IP cores, are announcing a strategic partnership to bring flexible and energy efficient Root-of-Trust security IP solution based on RISC-V to the industry.

Silex Insight’s advanced eSecure IP module is a complete solution that enables security applications by shielding confidential information from non-secure applications running on main processor along with security boot, sensitive key materials and assets protection. AndesCore™ N22, a high-efficiency and low-power 2-stage pipeline RISC-V CPU core, is tightly integrated in the eSecure IP module to fully and robustly control the execution of security functions. eSecure module is highly configurable and thus provides a wide-range selection of security features, performance, area and energy consumption that is suitable for many applications such as IoT, storage, and communication.

“We are able to deliver a ready-to-go solution to SoC makers who need advanced security and efficiency”, says Pieter Willems, Director Sales and Marketing Security Products at Silex Insight and he continues; “With Andes’ N22 RISC-V CPU core integrated in our eSecure Root-of-Trust turnkey solution, customers who demand high security on their devices can easily prevent hostile attacks from the outside world.”

“Root-of-Trust is now fundamental to many devices and connected services,” answers Dr. Charlie Su, CTO and Executive VP of Andes Technology. “We are excited to be able to deliver configurable and efficient security turnkey solution to SoC design companies, thanks to our ultra-compact RISC-V compliant processor N22, included in Silex Insight eSecure IP module platform.”

This robust secure solution is perfect for security-sensitive applications and it is available now from both Andes Technology and Silex Insight.

About Andes Technology

Andes Technology Corporation is a world class creator of innovative high-performance/low-power 32/64-bit processor cores and associated development environment to serve the rapidly growing global embedded system applications. The company delivers superior low power CPU cores, including the comprehensive RISC-V V5 family of processor cores, with integrated development environment and associated software/hardware solutions for efficient SoC design. Up to the end of 2018, the cumulative volume of Andes-Embedded™ SoCs has reached 3.5 billion with 2018 alone contributing over 1 billion. Andes Technology’s comprehensive CPU line includes entry-level, mid-range, high-end, extensible and security families. For more information, please visit www.andestech.com

About Silex Insight

Founded in 1991, Silex Insight is a recognized market-leading independent supplier Security IP solutions for embedded systems. The security platforms and solutions from Silex Insight include flexible  and high-performance crypto-engines which are easy to integrate and a eSecure IP module which provides a complete security solution for all platforms. Development and manufacturing take place at the headquarters near Brussels, Belgium. Local sales and support are handled by worldwide branch offices. For more information visit: www.silexinsight.com

PRESS CONTACT:

Andes Technology Corporation:               
Hsiao-Ling Lin
Marketing Manager
E: hllin@andestech.com
M:+886 3 5726533
Web: www.andestech.com

Silex Insight:
Jon Jacobsen
Marketing Manager
E: marketing@silexinsight.com
M: +32 475 50 30 37
Web: www.silexinsight.com

Continue ReadingAndes Technology and Silex Insight Announce Strategic Partnership for RISC-V Based Root-of-Trust IP Solutions