Frankwell Lin, President of Andes Technology, presented “Andes RISC-V CPU IP Provides Synergism for TSMC Process Portfolio” during the TSMC Europe open innovation platform (OIP) ecosystem forum in Amsterdam on May 27. The presentation described the open source RISC-V instruction set architecture synergy that RISC-V CPU IP provides to TSMC’s ecosystem. The speech was well received by the audience. Andes management and technical team were on hand throughout the day in the TSMC Europe Technology Symposium Exhibition area to describe Andes new RISC-V products and to answer questions from attendees. Andes demos included a face detection system with RISC-V based AndesCore™ AX25 embedded.