Andes’ Role in RISC-V Community
RISC-V ISA is an innovation for industry because it is open, compact, modular and extensible; also 64-bit is natively defined. However, RISC-V is merely an instruction set architecture. It needs microarchitecture implementation and other associated products (such as compiler, development tools, and platform) to provide complete CPU IP solution. Andes sees the potential of RISC-V. Andes is joining forces with partners of RISC-V community to grow the ecosystem by bringing Andes’ CPU IP experiences together with RISC-V’s technology:
- Andes becomes one of the founding members of RISC-V Foundation (2016)
- Andes is a RISC-V major tool-chain contributor (and maintainer).
- Andes will provide a complete product portfolio with RISC-V CPU IP. Andes is your reliable RISC-V core IP business partner.
- Andes provides world’s leading customer-instruction extension capable RISC-V core IP (Andes 25-series cores) and tool.
- Andes provides RISC-V cores that runs Linux.
- Through years of interaction with customers, Andes is professional in designing details important to SoCs.
Andes’ RISC-V Solutions
1. AndeStar™ V5 Architecture:
- V5 is the new family of AndeStar architecture which is fully compliant with RISC-V technology while bringing extended features unique to Andes and already proven in the V3 processors, such as
- Andes Performance Extension to speed up common program sequence such as those for memory accesses and branches
- Andes Custom Extension™ (ACE) to enable user-defined instructions for Domain-Specific Acceleration (DSA)
- CoDense™ for further code size compaction
- StackSafe™ stack overflow/underflow detection for program reliability
- PowerBrake frequency scaling for power saving.
- Supports both 32-bits (RV32) and 64-bits (RV64), and the latter is for applications demanding addressability greater than 4 GB or those benefiting from data wider than 32 bits.
Processors based on V5 architecture are supported by the same rich and easy-to-use environment as in V3 processors.
2. Facts of AndesCore™ N25F, NX25/NX25F, A25 and AX25 processors:
- Based on AndeStar™ V5 architecture:
- 32-bit N25, N25F and A25; 64-bit NX25, NX25F and AX25
- N25F, NX25F, A25 and AX25 supports single and double precision floating point for high-precision data computations
- D25F, A25 and AX25 supports DSP/SIMD instructions
- A25 and AX25 supports MMU (Memory Management Unit) for Linux applications
- Pipeline features:
- Fast: Dynamic Branch Prediction, Local Memory (LM) and Caches
- Operating above 1.1GHz with TSMC 28nm process
- Compact: 5-stage pipeline, many features are configurable as customer’s design requires
- Support Andes Custom Extension™ (ACE) for domain-specific acceleration
- Other key features including: ECC and parity for memory protection, configurable multiplier, well-balanced pipeline
- Platform-Level Interrupt Controller (PLIC): To meet the common requirements of microcontrollers and real-time applications, Andes enhanced RISC-V’s PLIC with vectored interrupt dispatch, and priority-based preemption for greatly reduced interrupt service latency and easier software programming
- Product package options: CPU subsystem pre-integrated with bus controller and AHB/AXI platforms to jump-start SoC design
3. Software development environment:
- Offer the best RISC-V compiler and most comprehensive GUI-based development environment
- Brings the production-proven methodology for instruction customization, ACE, to RISC-V world with a complete and easy-to-use toolset and verification framework.
- Unified development environment through the tens of thousands of installation base AndeSight IDE, to integrate supports for both mass-produced V3 processors and emerging V5 processors into one tool framework and also to ease migration works to RISC-V based ISA V5.
- Support the popular open source FreeRTOS version 10 and also the industrial-strength ThreadX on both 32-bit and 64-bit RISC-V processors. That’s the first 64-bit RISC-V enabled ThreadX port running on AndesCore NX25.
- Continuous contributions on RISC-V architecture port to gcc, binutils, newlib, qemu, LLVM, U-BOOT and Linux framework.
4. Hardware development environment:
- Full-featured FPGA development board
- Compact Arduino-compatible Corvette-F1 board
- ICE debugger
Ecosystem and Support
For the past 13 years, we have engaged over 120 partners from the fields including:
- Hardware: connectivity, security, mixed-signal, graphics, AI …
- Software: software stack, development tools, RTOS/middleware, voice processing…
- Development environments for complex SoC design
In addition, we also have knect.me ecosystem focusing on IoT :
- Over 50 partners, provides various IoT solutions such as security, wireless connectivity, protocol stacks, RTOS …
Andes is working together with many RISC-V Foundation members to provide an advanced development environment. For example, Imperas has fast Instruction Set Simulator (ISS) and Virtual Platform that enables software development before hardware is ready; Mentor, a Siemens Business, provides Veloce Emulator that reduces risk and shortens verification of complex SoCs; UltraSoC’s embedded run control and trace IP can help debug touch bugs and identify software bottlenecks; Lauterbach’s well-known Trace32 already supported Andes N25/NX25; Andes worked with Express Logic to port the first 64-bit ThreadX RTOS to RISC-V.More and more partners are joining Andes to rich RISC-V ecosystem together. We will update the list as we go!
Andes supports customers with a well-established support team that have years of experiences serving its customers.
Strengths and Track Records
- Andes is a public listed company in Taiwan Stock Exchange (March 2017)
- Andes was awarded with TSMC’s OIP “Partner of the Year” for New IP (2015)
- Andes has track record of over 140 commercial licensees and over 2.5B Andes-Embedded SoCs shipped.
- Andes sales and support channel covers Taiwan, China, Japan, Korea, United States, and Europe.
- There are multiple world class companies evaluating Andes N25/NX25 now.