Andes Technology Features 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors With Andes Custom Extension at TSMC 2019 Open Innovation Platform® Ecosystem Forum


A25MP and AX25MP are Cache Coherent RISC-V Multicore Processors
With Comprehensive DSP Instruction Extension and Custom Extensions for AI and ADAS Designs

HSINCHU, TAIWAN – September 24, 2019 – Andes Technology Corporation, a leading supplier of small, low-power, high performance 32/64-bit embedded CPU cores, including a broad family of RISC-V cores, announced that it will be participating in the TSMC 2019 Open Innovation Platform® Ecosystem Forum, on September 26, 2019 at the Santa Clara Convention Center. Andes Technology will feature its latest generation 32-bit A25MP and 64-bit AX25MP RISC-V Multicore Processors with Andes Custom Extensions, that allows designers to create special instructions to accelerate compute intensive functions, a capability highly desired in AI and ADAS designs. The cache coherent A25MP and AX25MP RISC-V multicore processors are the company’s first with comprehensive DSP instruction extension based on the RISC-V P-extension draft Andes donated to the RISC-V Foundation.

“The A25MP and AX25MP have already achieved major design wins in high-performance artificial intelligence applications and the product family has seen strong interest from Fortune 500 companies,” said Andes Technology Corp. President, Frankwell Lin. “Multiple processor cores extended with Andes Custom Extensions working in parallel enable computation intensive applications, such as artificial intelligence and Advanced Driver-Assistance Systems (ADAS) to significantly boost their performance. Furthermore, the DSP/SIMD ISA, executing the CIFAR-10 dataset (Canadian Institute For Advanced Research) image classification benchmark for machine learning achieved an order of magnitude performance boost. It also achieved 7 times acceleration in the PNET for MtCNN (Multi-task Cascaded Convolutional Networks) face detection and alignment algorithm.”

“The A25MP and AX25MP support up to four CPU cores,” said Dr. Charlie Su, CTO and EVP of Andes Technology Corp. “The processors’ hardware-managed cache coherence simplifies software design considerably for systems with multiple CPUs. They provide efficient cache coherence among private level-1 caches, include an optional shared level-2 cache and support I/O coherence for bus masters without caches. Besides that, using Andes Custom Extension™ (ACE) designers can increase performance by adding their own CPU instructions specifically for the target applications on the already optimized AndesCore™ processors and eliminate the software bottlenecks. Operating at over 1GHz in a 28nm process with Linux symmetric multiprocessing (SMP) support, the A25MP and AX25MP raise the RISC-V processors to the next performance level and widens its market potential.”

For more information about the A25MP/AX25MP multicores, please visit Andes Technology Corp. in booth 308 at TSMC 2019 Open Innovation Platform® Ecosystem Forum exhibition on September 26, 2019 at the Santa Clara Convention Center. In addition, please see Andes Technology Corp.’s presentation “Implementing Customized RISC-V CPUs in Machine Learning Applications,” in TSMC 2019 Open Innovation Platform® Ecosystem Forum printed proceedings. You can also learn about the A25MP and AX25MP cores as well as all Andes CPU core on our website