Quick-Start Design Package is a complete solution that significantly reduces time to market for SoC designs. The package includes the AndesCore™ N650 CPU IP, AndeShape™ AE100 Platform IP, and AndeSight™ MCU IDE software development environment. The N650 CPU IP provides the performance-efficiency needed for entry-level SoCs. It is the best candidate to replace 8051 and other 8-bit MCUs for small-footprint, cost- and power-sensitive applications. The AE100 Platform IP provides a light-weight base structure of SoC constructed by a configurable AHB Fabric with APB Bridge as well as several essential peripheral IPs. With AE100, users can easily build a low-cost SoC with high flexibility and fast time-to-market. All the AE100 components are designed to minimize the access latency, the logic gate count, and the power consumption. By pre-integrating and pre-verifying processor, fabric, and peripherals, the package jump-starts customer’s SoC projects with a solid foundation and reduces custom glue logic design teams need to create and verify.
AndesCore™ N650 CPU IP
|ATCMSTMUX100||AHB-Lite master multiplexer|
|ATCPIT100||Programmable interval timer|
|ATCRAMBRG200||Low-latency RAM bridge|
AndeSight IDE v2.1 MCU-N6