2018 Andes RISC-V CON

Time Topic Speaker
08:30~09:00 Registration
09:00-09:05 Opening
Frankwell Lin, President
Andes Technology
09:05-09:35 Roadmap Directions for the RISC-V Architecture
Linley Gwennap, President
The Linley Group
09:35-10:05 RISC-V from Mediatek’s Perspective Shichin Ouyang
10:05-10:20 Tea Break
10:20-11:00 Comprehensive RISC-V Solutions for AIoT Charlie Su, CTO & Senior VP
Andes Technology
11:00-11:45 Panel: Is RISC-V Ready for Your Design?
Moderator: Linley Gwennap
Panelist: Andes, Gowin, Imperas, MediaTek
11:45-12:10 Unleashing Chip Design Barrier With RISC-V Frankwell Lin, President
Andes Technology
12:10-13:40 Lunch
13:40-14:10 Ecosystem and Solutions for AIoT Emerson Hsiao, Senior VP
Andes Technology
14:10-14:40 How the RISC-V ISA can Speed SoC
Front End Design and Verification
Jeremy Ralph
14:40-15:20 Tea Break
15:20-16:00 RISC-V Microprocessor
Implementation for FPGA Solutions
16:00-16:30 Building a RISC-V Virtual Platform for
Rapid Embedded Software Development
16:30-17:00 Andes SW Solutions for RISC-V Justin Tseng,
VP of RD-VLSI and M&S Andes Technology
17:00~ Q&A